Table of Contents
Paragraph
Number
4.5.15.2
4.5.15.3
4.5.15.4
4.5.15.5
4.5.15.6
4.5.15.7
4.5.15.8
4.5.15.9
4.5.15.10
4.5.16
4.5.16.1
4.5.16.2
4.5.16.3
4.5.16.4
4.5.16.5
4.5.16.6
4.5.16.7
4.5.16.8
4.5.16.9
4.5.16.10
4.5.16.11
4.6
4.6.1
4.6.2
4.6.3
4.7
4.7.1
4.7.1.1
4.7.1.2
4.7.2
4.7.3
4.7.4
4.7.4.1
4.7.4.2
4.7.4.3
4.7.4.4
4.7.5
Title
Page
Number
x
MC68302 USER’S MANUAL
MOTOROLA
Rate Adaption of 48- and 56-kbps User Rates to 64 kbps...................4-116
Adaption for Asynchronous Rates up to 19.2 kbps..............................4-117
V.110 Controller Overview...................................................................4-117
V.110 Programming Model..................................................................4-118
Error-Handling Procedure....................................................................4-118
V.110 Receive Buffer Descriptor (Rx BD)............................................4-118
V.110 Transmit Buffer Descriptor (Tx BD) ...........................................4-120
V.110 Event Register...........................................................................4-121
V.110 Mask Register............................................................................4-122
Transparent Controller.........................................................................4-122
Transparent Channel Buffer Transmission Processing .......................4-123
Transparent Channel Buffer Reception Processing.............................4-124
Transparent Memory Map....................................................................4-125
Transparent Commands......................................................................4-126
Transparent Synchronization...............................................................4-126
Transparent Error-Handling Procedure................................................4-128
Transparent Mode Register.................................................................4-129
Transparent Receive Buffer Descriptor (RxBD)...................................4-130
Transparent Transmit Buffer Descriptor (Tx BD) .................................4-131
Transparent Event Register.................................................................4-133
Transparent Mask Register..................................................................4-134
Serial Communication Port (SCP) .......................................................4-134
SCP Programming Model....................................................................4-136
SCP Transmit/Receive Buffer Descriptor.............................................4-137
SCP Transmit/Receive Processing......................................................4-137
Serial Management Controllers (SMCs) ..............................................4-138
Overview..............................................................................................4-138
Using IDL with the SMCs.....................................................................4-138
Using GCI with the SMCs....................................................................4-138
SMC Programming Model....................................................................4-139
SMC Commands..................................................................................4-140
SMC Memory Structure and Buffers Descriptors.................................4-140
SMC1 Receive Buffer Descriptor.........................................................4-141
SMC1 Transmit Buffer Descriptor........................................................4-142
SMC2 Receive Buffer Descriptor.........................................................4-142
SMC2 Transmit Buffer Descriptor........................................................4-143
SMC Interrupt Requests ......................................................................4-143
Section 5
Signal Description
5.1
5.2
5.3
5.4
5.5
Functional Groups....................................................................................5-1
Power Pins...............................................................................................5-2
Clocks......................................................................................................5-4
System Control ........................................................................................5-5
Address Bus Pins (A23–A1) ....................................................................5-7