System Integration Block (SIB)
3-24
MC68302 USER’S MANUAL
MOTOROLA
3.2.5 Interrupt Controller Programming Model
The user communicates with the interrupt controller using four registers. The global interrupt
mode register (GIMR) defines the interrupt controller's operational mode. The interrupt
pending register (IPR) indicates which INRQ interrupt sources require interrupt service. The
interrupt mask register (IMR) allows the user to prevent any of the INRQ interrupt sources
from generating an interrupt request. The interrupt in-service register (ISR) provides a ca-
pability for nesting INRQ interrupt requests.
3.2.5.1 Global Interrupt Mode Register (GIMR)
The user normally writes the GIMR soon after a total system reset. The GIMR is initially
$0000 and is reset only upon a total system reset. If bits V7–V5 of the GIMR are not written
to specify an interrupt vector prior to the first interrupt condition, the interrupt controller will
pass the vector $0F (the uninitialized interrupt vector), regardless of the interrupt source.
MOD—Mode
0 = Normal operational mode. Interrupt request lines are configured as IPL2–IPL0.
1 = Dedicated operational mode. Interrupt request lines are configured as IRQ7, IRQ6,
and IRQ1.
IV7—Level 7 Interrupt Vector
This bit is valid in both normal and dedicated modes.
0 = Internal vector. The interrupt controller will provide the vector number for a level 7
interrupt during the interrupt acknowledge cycle.
1 = External vector. The interrupt controller will not provide the vector number for a lev-
el 7 interrupt.
IV6—Level 6 Interrupt Vector
This bit is valid in both normal and dedicated modes.
0 = Internal vector. The interrupt controller will provide the vector number for a level 6
interrupt during the interrupt acknowledge cycle.
1 = External vector. The interrupt controller will not provide the vector number for a lev-
el 6 interrupt.
IV1—Level 1 Interrupt Vector
This bit is valid in both normal and dedicated modes.
0 = Internal vector. The interrupt controller will provide the vector number for a level 1
interrupt acknowledge cycle.
1 = External vector. The interrupt controller will not provide the vector number for a lev-
el 1 interrupt.
15
14
13
12
11
10
9
8
7
5
4
0
MOD
IV7
IV6
IV1
—
ET7
ET6
ET1
V7–V5
RESERVED