參數資料
| 型號： | MC68306FC16B |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 135/191頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU INTEGRATED 132-PQFP |
| 標準包裝： | 36 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 16MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 供應商設備封裝： | 132-PQFP（24.13x24.13） |
| 包裝： | 托盤 |
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3- 16
MC68306 USER'S MANUAL
MOTOROLA
The timing diagram in Figure 3-14 shows that the bus request is negated at the time that
an acknowledge is asserted. This type of operation applies to a system consisting of a
processor and one other device capable of becoming bus master. In systems having
several devices that can be bus masters, bus request lines from these devices can be
wire-ORed at the processor, and more than one bus request signal could occur.
The bus grant signal is negated a few clock cycles after the assertion of the bus grant
acknowledge signal. However, if bus requests are pending, the processor reasserts bus
grant for another request a few clock cycles after bus grant (for the previous request) is
negated. In response to this additional assertion of bus grant, external arbitration circuitry
selects the next bus master before the current bus master has completed the bus activity.
The timing diagram in Figure 3-15 also applies to a system consisting of a processor and
one other device capable of becoming bus master. Since the 2-wire bus arbitration
scheme does not use a bus grant acknowledge signal, the external master must continue
to assert BR until it has completed its bus activity. The processor negates bus grant when
BR is negated.
3.2.1 Requesting the Bus
External devices capable of becoming bus masters assert BR to request the bus. This
signal can be wire-ORed (not necessarily constructed from open-collector devices) from
any of the devices in the system that can become bus master. The processor, which is at
a lower bus priority level than the external devices, relinquishes the bus after it completes
the current bus cycle.
3.2.2 Receiving the Bus Grant
The processor asserts BG as soon as possible. Normally, this process immediately
follows internal synchronization, except when the processor has made an internal decision
to execute the next bus cycle but has not yet asserted AS for that cycle. In this case, BG is
delayed until AS is asserted to indicate to external devices that a bus cycle is in progress.
BG can be routed through a daisy-chained network or through a specific priority-encoded
network. Any method of external arbitration that observes the protocol can be used.
3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only)
Upon receiving BG , the requesting device waits until AS, DTACK, and BGACK are
negated before asserting BGACK. The negation of AS indicates that the previous bus
master has completed its cycle. (No device is allowed to assume bus mastership while AS
is asserted.) The negation of BGACK indicates that the previous master has released the
bus. The negation of DTACK indicates that the previous slave has terminated the
connection to the previous master. (In some applications, DTACK might not be included in
this function; general-purpose devices would be connected using AS only.) When BGACK
is asserted, the asserting device is bus master until it negates BGACK . BGACK should not
be negated until after the bus cycle(s) is complete. A device relinquishes control of the bus
by negating BGACK .
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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