參數(shù)資料
型號: MC68331CAG25
廠商: Freescale Semiconductor
文件頁數(shù): 22/84頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 25MHZ 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: M683xx
核心處理器: CPU32
芯體尺寸: 32-位
速度: 25MHz
連通性: EBI/EMI,SCI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
MC68331TS/D
29
Figure 9 Chip-Select Circuit Block Diagram
The following table lists allocation of chip-selects and discrete outputs on the pins of the MCU.
3.5.1 Chip-Select Registers
Pin assignment registers CSPAR0 and CSPAR1 determine functions of chip-select pins. These regis-
ters also determine port size (8- or 16-bit) for dynamic bus allocation.
A pin data register (PORTC) latches discrete output data.
Blocks of addresses are assigned to each chip-select function. Block sizes of 2 Kbytes to 1 Mbyte can
be selected by writing values to the appropriate base address register (CSBAR). Address blocks for
separate chip-select functions can overlap.
Chip-select option registers (CSORBT and CSOR[10:0]) determine timing of and conditions for asser-
tion of chip-select signals. Eight parameters, including operating mode, access size, synchronization,
and wait state insertion can be specified.
Initialization code often resides in a peripheral memory device controlled by the chip-select circuits. A
set of special chip-select functions and registers (CSORBT, CSBARBT) is provided to support bootstrap
operation.
Pin
Chip Select
Discrete Outputs
CSBOOT
BR
CS0
BG
CS1
BGACK
CS2
FC0
CS3
PC0
FC1
CS4
PC1
FC2
CS5
PC2
ADDR19
CS6
PC3
ADDR20
CS7
PC4
ADDR21
CS8
PC5
ADDR22
CS9
PC6
ADDR23
CS10
ECLK
CHIP SEL BLOCK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
BASE ADDRESS REGISTER
TIMING
AND
CONTROL
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
AVEC
DSACK
PIN
BUS CONTROL
INTERNAL
SIGNALS
ADDRESS
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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