MC68331
USER’S MANUAL
OVERVIEW
MOTOROLA
3-9
3
Data Strobe
DS
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
Provide asynchronous data transfers and dynamic bus sizing
Serial I/O and clock for background debugging mode
Data and Size Acknowledge
Development Serial In, Out, Clock
DSACK[1:0]
DSI, DSO,
DSCLK
EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an
external oscillator can be used
FC[2:0]
Identify processor state and current address space
FREEZE
Indicates that the CPU has entered background mode
HALT
Suspend external bus activity
IC[3:1]
When a specified transition is detected on an input capture pin, the
value in an internal GPT counter is latched
IC4/OC5
Can be configured for either an input capture or output compare
Crystal Oscillator
Function Codes
Freeze
Halt
Input Capture
Input Capture 4/
Output Compare 5
Instruction Pipeline
Interrupt Request Level
Master In Slave Out
IPIPE, IFETCH Indicate instruction pipeline activity
IRQ[7:1]
Provides an interrupt priority level to the CPU
MISO
Serial input to QSPI in master mode; serial output from QSPI in
slave mode
MODCLK
Selects the source and type of system clock
MOSI
Serial output from QSPI in master mode; serial input to QSPI in
slave mode
OC[5:1]
Change state when the value of an internal GPT counter matches
a value stored in a GPT control register
PAI
Signal input to the pulse accumulator
PC[6:0]
SIM digital output port signals
PCLK
External clock dedicated to the GPT
PCS[3:0]
QSPI peripheral chip selects
PE[7:0]
SIM digital I/O port signals
PF[7:0]
SIM digital I/O port signals
PGP[7:0]
GPT digital I/O port signals
PQS[7:0]
QSM digital I/O port signals
PWMA, PWMB Output for PWM
QUOT
Provides the quotient bit of the polynomial divider
RESET
System reset
RMC
Indicates an indivisible read-modify-write instruction
R/W
Indicates the direction of data transfer on the bus
RXD
Serial input to the SCI
SCK
Clock output from QSPI in master mode; clock input to QSPI in
slave mode
SIZ[1:0]
Indicates the number of bytes to be transferred during a bus cycle
SS
Causes serial transmission when QSPI is in slave mode; causes
mode fault in master mode
TSC
Places all output drivers in a high-impedance state
TXD
Serial output from the SCI
XFC
Connection for external phase-locked loop filter capacitor
Clock Mode Select
Master Out Slave In
Output Compare
Pulse Accumulator Input
Port C
Auxiliary Timer Clock Input
Peripheral Chip Select
Port E
Port F
Port GP
Port QS
Pulse-Width Modulation
Quotient Out
Reset
Read-Modify-Write Cycle
Read/Write
SCI Receive Data
QSPI Serial Clock
Size
Slave Select
Three-State Control
SCI Transmit Data
External Filter Capacitor
Table 3-5 Signal Function (Continued)
Signal Name
Mnemonic
Function