- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45211 > MC68331MFC16 (FREESCALE SEMICONDUCTOR INC) 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP132 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68331MFC16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 50/254頁(yè) |
| 文件大小： | 1366K |
| 代理商： | MC68331MFC16 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)當(dāng)前第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)
MC68331
QUEUED SERIAL MODULE
MOTOROLA
USER’S MANUAL
6-17
6
Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock
on the SPI bus master supplies the clock signal (SCK) to time the transfer of data. Four
possible combinations of clock phase and polarity can be specified by the CPHA and
CPOL bits in SPCR0.
Data is transferred with the most significant bit first. The number of bits transferred per
command defaults to eight, but can be set to any value from eight to sixteen bits by
writing a value into the BITSE field in command RAM.
Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the
system. If needed, the WOMQ bit in SPCR0 can be set to provide wired-OR, open-
drain outputs. An external pull-up resistor should be used on each output line. WOMQ
affects all QSPI pins regardless of whether they are assigned to the QSPI or used as
general-purpose I/O.
6.3.5.1 Master Mode
Setting the MSTR bit in SPCR0 selects master mode operation. In master mode, the
QSPI can initiate serial transfers, but cannot respond to externally initiated transfers.
When the slave select input of a device configured for master mode is asserted, a
mode fault occurs.
Before QSPI operation is initiated, QSM register PQSPAR must be written to assign
necessary pins to the QSPI. The pins necessary for master mode operation are MISO
and MOSI, SCK, and one or more of the chip-select pins. MISO is used for serial data
input in master mode, and MOSI is used for serial data output. Either or both may be
necessary, depending on the particular application. SCK is the serial clock output in
master mode.
Before master mode operation is initiated, QSM register DDRQS must be written to
direct the data flow on the QSPI pins used. Configure the SCK, MOSI and appropriate
chip-select pins PCS[3:0]/SS as outputs. The MISO pin must be configured as an in-
put.
After pins are assigned and configured, write appropriate data to the command queue.
If data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers
as appropriate.
Data transfer is synchronized with the internally-generated serial clock (SCK). Control
bits, CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of
CPHA and CPOL determine upon which SCK edge to drive outgoing data from the
MOSI pin and to latch incoming data from the MISO pin.
Baud rate is selected by writing a value from 2 to 255 into the SPBR field in SPCR0.
The QSPI uses a modulus counter to derive SCK baud rate from the MCU system
clock.
The following expressions apply to SCK baud rate:
SCK Baud Rate
System Clock
2
SPBR
×
------------------------------------
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68331CFC16 | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP132 |
| MC68332GCPV16 | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP144 |
| MC68332GVPV25 | 32-BIT, 25 MHz, MICROCONTROLLER, PQFP144 |
| MC68332GVFC25 | 32-BIT, 25 MHz, MICROCONTROLLER, PQFP132 |
| MC68332GCPV20 | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68331MFC20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:User’s Manual |
| MC68331MFV16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:User’s Manual |
| MC68331MFV20 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68331MPV16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:User’s Manual |
| MC68331MPV20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:User’s Manual |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。