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參數(shù)資料
| 型號： | MC68331MFC20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | User’s Manual |
| 中文描述： | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 212/254頁 |
| 文件大?。?/td> | 1354K |
| 代理商： | MC68331MFC20 |
MOTOROLA
D-4
REGISTER SUMMARY
MC68331
USER’S MANUAL
D
D.2 General-Purpose Timer
Table D-2
displays the GPT address map.
The column labeled “Access” indicates the
privilege level at which the CPU must be operating to access the register. A designa-
tion of “S” indicates that supervisor access is required: a designation of “S/U” indicates
that the register can be programmed to the desired privilege level.
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D.2.1 GPTMCR
— GPT Module Configuration Register
$YFF900
GPTMCR bits control freeze, low-power stop, and single-step modes.
STOP — Stop Clocks
0 = Internal clocks not shut down
1 = Internal clocks shut down
Table D-2 GPT Address Map
Access
S
S
S
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
Address
$YFF900
$YFF902
$YFF904
$YFF906
$YFF908
$YFF90A
$YFF90C
$YFF90E
$YFF910
$YFF912
$YFF914
$YFF916
$YFF918
$YFF91A
$YFF91C
$YFF91E
$YFF920
$YFF922
$YFF924
$YFF926
$YFF928
$YFF92A
$YFF92C
$YFF92E –
$YFF93F
15
8 7
0
GPT MODULE CONFIGURATION (GPTMCR)
(RESERVED FOR TEST)
INTERRUPT CONFIGURATION (ICR)
PGP DATA DIRECTION (DDRGP)
OC1 ACTION MASK (OC1M)
TIMER COUNTER (TCNT)
PA CONTROL (PACTL)
INPUT CAPTURE 1 (TIC1)
INPUT CAPTURE 2 (TIC2)
INPUT CAPTURE 3 (TIC3)
OUTPUT COMPARE 1 (TOC1)
OUTPUT COMPARE 2 (TOC2)
OUTPUT COMPARE 3 (TOC3)
OUTPUT COMPARE 4 (TOC4)
INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)
TIMER CONTROL 1 (TCTL1)
TIMER MASK 1 (TMSK1)
TIMER FLAG 1 (TFLG1)
FORCE COMPARE (CFORC)
PWM CONTROL A (PWMA)
PWM COUNT (PWMCNT)
PWMA BUFFER (PWMBUFA)
GPT PRESCALER (PRESCL)
NOT USED
PGP DATA (PORTGP)
OC1 ACTION DATA (OC1D)
PA COUNTER (PACNT)
TIMER CONTROL 2 (TCTL2)
TIMER MASK 2 (TMSK2)
TIMER FLAG 2 (TFLG2)
PWM CONTROL C (PWMC)
PWM CONTROL B (PWMB)
PWMB BUFFER (PWMBUFB)
15
14
13
12
11
10
9
8
7
6
5
4
3
0
STOP
FRZ1
FRZ0
STOPP
INCP
0
0
0
SUPV
0
0
0
IARB
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
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