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| 型號(hào)： | MC68331VPV20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | User’s Manual |
| 中文描述： | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 129/254頁(yè) |
| 文件大小： | 1354K |
| 代理商： | MC68331VPV20 |
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MC68331
USER’S MANUAL
QUEUED SERIAL MODULE
MOTOROLA
6-3
6
then setting STOP after the HALTA flag is set. Refer to
SECTION 4 SYSTEM INTE-
GRATION MODULE
for more information about low-power operation.
6.2.1.2 Freeze Operation
The freeze (FRZ[1:0]) bits in the QSMCR are used to determine what action is taken
by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the
CPU enters background debugging mode. At the present time, FRZ0 has no effect;
setting FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE
assertion. Refer to
SECTION 5 CENTRAL PROCESSING UNIT
for more information
about background debugging mode.
6.2.1.3 QSM Interrupts
Both the QSPI and SCI can make interrupt requests on the IMB. Each has a separate
interrupt request priority register, but a single vector register is used to generate ex-
ception vector numbers.
The values of the ILQSPI and ILSCI fields in the QILR determine the priority of QSPI
and SCI interrupt requests. The values in these fields correspond to internal interrupt
request signals IRQ[7:1]. A value of %111 causes IRQ7 to be asserted when a QSM
interrupt request is made; lower field values cause corresponding lower-numbered in-
terrupt request signals to be asserted. Setting field value to %000 disables interrupts.
If ILQSPI and ILSCI have the same nonzero value, and the QSPI and SCI make simul-
taneous interrupt requests, the QSPI has priority.
When the CPU32 acknowledges an interrupt request, it places the value in the inter-
rupt priority (IP) mask in the CPU status register on the address bus. The QSM com-
pares IP mask value to request priority to determine whether it should contend for
arbitration priority. Arbitration priority is determined by the value of the IARB field in the
QSMCR. Each module that generates interrupts must have a nonzero IARB value. Ar-
bitration is performed by means of serial assertion of IARB field bit values.
When the QSM wins interrupt arbitration, it responds to the CPU interrupt acknowl-
edge cycle by placing an interrupt vector number on the data bus. The vector number
is used to calculate displacement into the CPU32 exception vector table. SCI and
QSPI vector numbers are generated from the value in the QIVR INTV field. The values
of bits INTV[7:1] are the same for QSPI and SCI, but the value of INTV0 is supplied by
the QSM when an interrupt request is made. INTV0 = 0 for SCI interrupt requests;
INTV0 = 1 for QSPI requests.
At reset, INTV is initialized to $0F, the uninitialized interrupt vector number. To enable
interrupt-driven serial communication, a user-defined vector number ($40–$FF) must
be written to QIVR, and interrupt handler routines must be located at the addresses
pointed to by the corresponding vector. CPU writes to INTV0 have no meaning or ef-
fect. Reads of INTV0 return a value of one.
Refer to
SECTION 5 CENTRAL PROCESSING UNIT
and
SECTION 4 SYSTEM IN-
TEGRATION MODULE
for more information about exceptions and interrupts.
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| MC68331CFV16 | User’s Manual |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68332 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Technical Supplement |
| MC683326CFC16 | 制造商:Motorola Inc 功能描述: |
| MC68332ACAG16 | 功能描述:32位微控制器 - MCU 32B MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MC68332ACAG16 | 制造商:Freescale Semiconductor 功能描述:32-Bit Microcontroller IC |
| MC68332ACAG16B1 | 制造商:Freescale Semiconductor 功能描述: |
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