參數(shù)資料
型號: MC68332ACFC20
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-Bit Modular Microcontroller
中文描述: 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP132
封裝: PLASTIC, QFP-132
文件頁數(shù): 13/88頁
文件大小: 446K
代理商: MC68332ACFC20
MC68332
MC68332TS/D
MOTOROLA
13
2.5 Signal Function
TSC
TXD
XFC
XTAL
SIM
QSM
SIM
SIM
Input
Output
Input
Output
Table 6 MCU Signal Function
Signal Name
Mnemonic
ADDR[23:0]
AS
AVEC
BERR
BG
BGACK
BKPT
BR
CLKOUT
CS[10:0]
CSBOOT
DATA[15:0]
DS
Function
Address Bus
Address Strobe
Autovector
Bus Error
Bus Grant
Bus Grant Acknowledge
Breakpoint
Bus Request
System Clockout
Chip Selects
Boot Chip Select
Data Bus
Data Strobe
24-bit address bus
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Indicates that an external device requires bus mastership
System clock output
Select external devices at programmed addresses
Chip select for external boot start-up ROM
16-bit data bus
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle, indi-
cates that valid data is on the data bus.
Provide asynchronous data transfers and dynamic bus sizing
Serial I/O and clock for background debugging mode
Data and Size Acknowledge
Development Serial In, Out,
Clock
Crystal Oscillator
DSACK[1:0]
DSI, DSO,
DSCLK
EXTAL, XTAL
Connections for clock synthesizer circuit reference;
a crystal or an external oscillator can be used
Identify processor state and current address space
Indicates that the CPU has entered background mode
Suspend external bus activity
Indicate instruction pipeline activity
Function Codes
Freeze
Halt
Instruction Pipeline
FC[2:0]
FREEZE
HALT
IFETCH
IPIPE
IRQ[7:1]
MISO
Interrupt Request Level
Master In Slave Out
Provides an interrupt priority level to the CPU
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Selects the source and type of system clock
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
SIM digital output port signals
QSPI peripheral chip selects
SIM digital I/O port signals
SIM digital I/O port signals
QSM digital I/O port signals
Clock Mode Select
Master Out Slave In
MODCLK
MOSI
Port C
Peripheral Chip Select
Port E
Port F
Port QS
PC[6:0]
PCS[3:0]
PE[7:0]
PF[7:0]
PQS[7:0]
Table 5 MCU Signal Characteristics (Continued)
Signal Name
MCU Module
Signal Type
Active State
相關(guān)PDF資料
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MC68332ACFV16 32-Bit Modular Microcontroller
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