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參數(shù)資料
| 型號： | MC68332AVEH25 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 11/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 25MHZ 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 25MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 15 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 733 (CN2011-ZH PDF) |
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MC68332
MOTOROLA
MC68332TS/D
19
EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters con-
tinue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are dis-
abled, preventing interrupts during software debug.
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SLVEN — Factory Test Mode Enabled
This bit is a read-only status bit that reflects the state of DATA11 during reset.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] — Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer operations. A
show cycle allows internal transfers to be externally monitored. The table below shows whether show
cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict,
external peripherals must not be enabled during show cycles.
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor or user data space.
0 = Registers with access controlled by the SUPV bit are accessible from either the user or super-
visor privilege level.
1 = Registers with access controlled by the SUPV bit are restricted to supervisor access only.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 –$7FFFFF.
1 = Internal modules are addressed from $FFF000 –$FFFFFF.
IARB[3:0] — Interrupt Arbitration Field
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request. An IARB field must have a non-zero value for contention to take place.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU pro-
cesses a spurious interrupt exception. Because the SIM routes external interrupt requests to the CPU,
the SIM IARB field value is used for arbitration between internal and external interrupts of the same pri-
ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is
%0000, which prevents SIM interrupts from being discarded during initialization.
SHEN
Action
00
Show cycles disabled, external arbitration enabled
01
Show cycles enabled, external arbitration disabled
10
Show cycles enabled, external arbitration enabled
11
Show cycles enabled, external arbitration enabled,
internal activity is halted by a bus grant
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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