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| 型號： | MC68332GCEH25 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 64/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 25MHZ 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 180 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 25MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 15 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68332
MOTOROLA
MC68332TS/D
67
The system software must stop each submodule before asserting STOP to avoid complications at re-
start and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and
the operation should be verified for completion before asserting STOP. The QSPI submodule should be
stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set.
FRZ1 — Freeze 1
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted.
FREEZE is asserted whenever the CPU enters the background mode.
FRZ0 — Freeze 0
Reserved
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted
0 = User access
1 = Supervisor access
SUPV defines the assignable QSM registers as either supervisor-only data space or unrestricted data
space.
IARB — Interrupt Arbitration Identification Number
The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each
module that can generate interrupt requests must be assigned a unique, non-zero IARB field value. Re-
fer to 3.8 Interrupts for more information.
QTEST — QSM Test Register
$YFFC02
QTEST is used during factory testing of the QSM. Accesses to QTEST must be made while the MCU
is in test mode.
QILR determines the priority level of interrupts requested by the QSM and the vector used when an in-
terrupt is acknowledged.
ILQSPI — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
ILSCI — Interrupt Level of SCI
ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts
disabled) to $7 (highest priority).
If ILQSPI and ILSCI are the same nonzero value, and both submodules simultaneously request inter-
rupt service, QSPI has priority.
QILR — QSM Interrupt Levels Register
$YFFC04
15
14
13
11
10
8
7
0
ILQSPI
ILSCI
QIVR
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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