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參數(shù)資料
| 型號： | MC68332GVEH25 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 84/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 25MHZ 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 25MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 15 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 733 (CN2011-ZH PDF) |
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MC68332
MOTOROLA
MC68332TS/D
85
RASP — RAM Array Space Field
0 = TPURAM array is placed in unrestricted space
1 = TPURAM array is placed in supervisor space
TRAMTST — TPURAM Test Register
$YFFB02
TRAMTST is used for factory testing of the TPURAM module.
ADDR[23:11] — RAM Array Base Address
These bits specify address lines ADDR[23:11] of the base address of the RAM array when enabled.
RAMDS — RAM Array Disable
0 = RAM array is enabled
1 = RAM array is disabled
The RAM array is disabled by internal logic after a master reset. Writing a valid base address to the
RAM array base address field (bits [15:3]) automatically clears RAMDS, enabling the RAM array.
7.4 TPURAM Operation
There are six TPURAM operating modes, as follows:
1.
The TPURAM module is in normal mode when powered by VDD. The array can be accessed
by byte, word, or long word. A byte or aligned word (high-order byte is at an even address) ac-
cess only takes one bus cycle or two system clocks. A long word or misaligned word access
requires two bus cycles.
2.
Standby mode is intended to preserve TPURAM contents when VDD is removed. TPURAM
contents are maintained by VSTBY. Circuitry within the TPURAM module switches to the higher
of VDD or VSTBY with no loss of data. When TPURAM is powered by VSTBY, access to the array
is not guaranteed.
3.
Reset mode allows the CPU to complete the current bus cycle before resetting. When a syn-
chronous reset occurs while a byte or word TPURAM access is in progress, the access will be
completed. If reset occurs during the first word access of a long-word operation, only the first
word access will be completed. If reset occurs during the second word access of a long word
operation, the entire access will be completed. Data being read from or written to the RAM may
be corrupted by asynchronous reset.
4.
Test mode functions in conjunction with the SIM test functions. Test mode is used during factory
test of the MCU.
5.
Writing the STOP bit of TRAMMCR causes the TPURAM module to enter stop mode. The
TPURAM array is disabled (which allows external logic to decode TPURAM addresses, if nec-
essary), but all data is retained. If VDD falls below VSTBY during stop mode, internal circuitry
switches to VSTBY, as in standby mode. Stop mode is exited by clearing the STOP bit.
6.
The TPURAM array may be used to emulate the microcode ROM in the TPU module. This pro-
vides a means of developing custom TPU code. The TPU selects TPU emulation mode. While
in TPU emulation mode, the access timing of the TPURAM module matches the timing of the
TPU microinstruction ROM to ensure accurate emulation. Normal accesses via the IMB are in-
hibited and the control registers have no effect, allowing external RAM to emulate the TPURAM
at the same addresses.
TRAMBAR — TPURAM Base Address and Status Register
$YFFB04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
NOT USED
RAMDS
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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