參數(shù)資料
型號(hào): MC68332GVFV20
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-Bit Modular Microcontroller
中文描述: 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP144
封裝: QFP-144
文件頁(yè)數(shù): 47/88頁(yè)
文件大?。?/td> 446K
代理商: MC68332GVFV20
MC68332
MC68332TS/D
MOTOROLA
47
4.6 Instruction Set Summary
Table 20 Instruction Set Summary
Instruction
ABCD
Syntax
Dn, Dn
(An),
(An)
Dn, <ea>
<ea>, Dn
<ea>, An
#<data>, <ea>
# <data>, <ea>
Dn, Dn
(An),
(An)
<ea>, Dn
Dn, <ea>
# <data>, <ea>
# <data>, CCR
# <data>, SR
Dn, Dn
# <data>, Dn
<ea>
Dn, Dn
# <data>, Dn
<ea>
Operand Size
8
8
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
Operation
Source
10
+
Destination
10
+
X
Destination
ADD
Source
+
Destination
Destination
ADDA
ADDI
ADDQ
ADDX
Source
+
Destination
Destination
Immediate data
+
Destination
Destination
Immediate data
+
Destination
Destination
Source
+
Destination
+
X
Destination
AND
Source
Destination
Destination
ANDI
Data
Destination
Destination
Source
CCR
CCR
Source
SR
SR
ANDI to CCR
ANDI to SR1
1
ASL
ASR
Bcc
BCHG
label
Dn, <ea>
# <data>, <ea>
Dn, <ea>
# <data>, <ea>
8, 16, 32
8, 32
8, 32
8, 32
8, 32
If condition true, then PC
+
d
PC
BCLR
0
bit of destination
If background mode enabled, then enter background
mode, else format/vector
(SSP);
PC
(SSP); SR
(SSP); (vector)
PC
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal instruction
PC
+
d
PC
BGND
none
none
BKPT
# <data>
none
BRA
BSET
label
Dn, <ea>
# <data>, <ea>
8, 16, 32
8, 32
8, 32
1
bit of destination
SP
4
SP; PC
(SP); PC
+
d
PC
BSR
BTST
label
Dn, <ea>
# <data>, <ea>
<ea>, Dn
<ea>, Rn
8, 16, 32
8, 32
8, 32
16, 32
8, 16, 32
CHK
CHK2
If Dn < 0 or Dn > (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
0
Destination
(Destination
Source), CCR shows results
(Destination
Source), CCR shows results
(Destination
Data), CCR shows results
(Destination
Source), CCR shows results
Lower bound
Rn
Upper bound, CCR shows result
CLR
CMP
CMPA
CMPI
CMPM
CMP2
<ea>
<ea>, Dn
<ea>, An
# <data>, <ea>
(An)
+
, (An)
+
<ea>, Rn
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
X/C
0
X/C
bit number
of destination
)
Z
bit of destinatio
bit number
of destination
(
)
bit number
of destination
(
)
Z;
bit number
of destination
(
)
Z
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