MOTOROLA
48
MC68332
MC68332TS/D
DBcc
Dn, label
16
If condition false, then Dn
1
PC;
if Dn
≠
(
1), then PC
+
d
PC
Destination / Source
Destination
(signed or unsigned)
DIVS/DIVU
<ea>, Dn
32/16
16 : 16
DIVSL/DIVUL
<ea>, Dr : Dq
<ea>, Dq
<ea>, Dr : Dq
Dn, <ea>
# <data>, <ea>
# <data>, CCR
# <data>, SR
Rn, Rn
Dn
Dn
Dn
none
64/32
32 : 32
32/32
32
32/32
32 : 32
8, 16, 32
8, 16, 32
8
16
32
8
16
16
32
8
32
none
Destination / Source
Destination
(signed or unsigned)
EOR
EORI
Source
⊕
Destination
Destination
Data
⊕
Destination
Destination
Source
⊕
CCR
CCR
Source
⊕
SR
SR
Rn
Rn
EORI to CCR
EORI to SR
1
EXG
EXT
Sign extended Destination
Destination
EXTB
ILLEGAL
Sign extended Destination
Destination
SSP
2
SSP; vector offset
(SSP);
SSP
4
SSP; PC
(SSP);
SSP
2
SSP; SR
(SSP);
Illegal instruction vector address
PC
Destination
PC
SP
4
SP; PC
(SP); destination
PC
<ea>
An
SP
4
SP, An
(SP); SP
An, SP
+
d
SP
Data
SR; interrupt mask
EBI; STOP
JMP
JSR
LEA
LINK
LPSTOP
1
LSL
<ea>
<ea>
<ea>, An
An, # d
# <data>
Dn, Dn
# <data>, Dn
<ea>
Dn, Dn
#<data>, Dn
<ea>
<ea>, <ea>
<ea>, An
USP, An
An, USP
CCR, <ea>
<ea>, CCR
SR, <ea>
<ea>, SR
USP, An
An, USP
Rc, Rn
Rn, Rc
list, <ea>
<ea>, list
Dn, (d16, An)
none
none
32
16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
16, 32
32
32
32
16
16
16
16
32
32
32
32
16, 32
16, 32
32
16, 32
LSR
MOVE
MOVEA
MOVEA
1
Source
Destination
Source
Destination
USP
An
An
USP
CCR
Destination
Source
CCR
SR
Destination
Source
SR
USP
An
An
USP
Rc
Rn
Rn
Rc
Listed registers
Destination
Source
Listed registers
Dn [31 : 24]
(An
+
d); Dn [23 : 16]
(An
+
d
+
2);
Dn [15 : 8]
(An
+
d
+
4); Dn [7 : 0]
(An
+
d
+
6)
MOVE from CCR
MOVE to CCR
MOVE from SR
1
MOVE to SR
1
MOVE USP
1
MOVEC
1
MOVEM
MOVEP
(d16, An), Dn
(An
+
d)
Dn [31 : 24]; (An
+
d
+
2)
Dn [23 : 16];
(An
+
d
+
4)
Dn [15 : 8]; (An
+
d
+
6)
Dn [7 : 0]
Immediate data
Destination
MOVEQ
#<data>, Dn
8
32
Table 20 Instruction Set Summary(Continued)
Instruction
Syntax
Operand Size
Operation
X/C
0
X/C
0