參數(shù)資料
型號: MC68334GCEH16
廠商: Freescale Semiconductor
文件頁數(shù): 13/76頁
文件大?。?/td> 0K
描述: IC MCU 16MHZ 2K RAM 132-PQFP
標準包裝: 36
系列: M683xx
核心處理器: CPU32
芯體尺寸: 32-位
速度: 16MHz
連通性: EBI/EMI,UART/USART
輸入/輸出數(shù): 47
程序存儲器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 8x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 132-BQFP 緩沖式
包裝: 托盤
MC68334
20
MC68334TS/D REV. 1
Figure 7 System Clock Oscillator Circuit
If an external reference signal or an external system clock signal is applied via the EXTAL pin, the XTAL
pin must be left floating. External reference signal frequency must be less than or equal to maximum
specified reference frequency. External system clock signal frequency must be less than or equal to
maximum specified system clock frequency.
When an external system clock signal is applied (PLL disabled, MODCLK = 0 during reset), the duty
cycle of the input is critical, especially at operating frequencies close to maximum. The relationship be-
tween clock signal duty cycle and clock signal period is expressed:
Minimum External Clock Period =
3.3.2 Clock Synthesizer Operation
VDDSYN is used to power the clock circuits when either an internal or an external reference frequency
is applied. A separate power source increases MCU noise immunity and can be used to run the clock
when the MCU is powered down. A quiet power supply must be used as the VDDSYN source. Adequate
external bypass capacitors should be placed as close as possible to the VDDSYN pin to assure stable
operating frequency. When an external system clock signal is applied and the PLL is disabled, VDDSYN
should be connected to the VDD supply. Refer to the SIM Reference Manual (SIMRM/AD) for more in-
formation regarding system clock power supply conditioning.
A voltage controlled oscillator (VCO) generates the system clock signal. To maintain a 50% clock duty
cycle, VCO frequency is either two or four times system clock frequency, depending on the state of the
X bit in SYNCR. A portion of the clock signal is fed back to a divider/counter. The divider controls the
frequency of one input to a phase comparator. The other phase comparator input is a reference signal,
either from the crystal oscillator or from an external source. The comparator generates a control signal
proportional to the difference in phase between the two inputs. The signal is low-pass filtered and used
to correct VCO output frequency.
Filter geometry can vary, depending upon the external environment and required clock stability. The fig-
ure below shows two recommended filters. XFC pin leakage must be kept within specified limits to main-
tain optimum stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external system clock signal
is applied and the PLL is disabled. The XFC pin must be left floating in this case.
VSSI
EXTAL
XTAL
22 pF
*
C1
330k
R1
32 OSCILLATOR
RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-kHz CRYSTAL.
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
*
22 pF
*
C2
Minimum External Clock High Low Time
§
50% Percentage Variation of External Clock Input Duty Cycle
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
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相關代理商/技術參數(shù)
參數(shù)描述
MC68334GCEH16 制造商:Freescale Semiconductor 功能描述:Microcontroller
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