參數(shù)資料
型號(hào)： MC68334GVFC16
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 16 MHz, MICROCONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁數(shù)： 53/76頁
文件大?。?/td> 444K
代理商： MC68334GVFC16
MC68334
MOTOROLA
MC68334TS/D REV. 1
57
5.6.8 Brushless Motor Commutation (COMM)
This function generates the phase commutation signals for a variety of brushless motors, including
three-phase brushless direct current. It derives the commutation state directly from the position decod-
ed in FQD, thus eliminating the need for hall effect sensors.
The state sequence is implemented as a user-configurable state machine, thus providing a flexible ap-
proach with other general applications. A CPU offset parameter is provided to allow all the switching
angles to be advanced or retarded on the fly by the CPU. This feature is useful for torque maintenance
at high speeds.
5.6.9 Frequency Measurement (FQM)
FQM counts the number of input pulses to a TPU channel during a user-defined window period. The
function has single shot and continuous modes. No pulses are lost between sample windows in contin-
uous mode. The user selects whether to detect pulses on the rising or falling edge. This function is in-
tended for high speed measurement; measurement of slow pulses with noise rejection can be made
with PTA.
5.6.10 Hall Effect Decode (HALLD)
This function decodes the sensor signals from a brushless motor, along with a direction input from the
CPU, into a state number. The function supports two- or three-sensor decoding. The decoded state
number is written into a COMM channel, which outputs the required commutation drive signals. In ad-
dition to brushless motor applications, the function can have more general applications, such as decod-
ing “option” switches.
5.7 TPU Registers
The TPU memory map contains three groups of registers:
System Configuration Registers
Channel Control and Status Registers
Development Support and Test Verification Registers
5.7.1 System Configuration Registers
STOP — Stop Bit
0 = TPU operating normally
1 = Internal clocks shut down
TCR1P — Timer Count Register 1 Prescaler Control
TCR1 is clocked from the output of a prescaler. The prescaler's input is the internal TPU system clock
divided by either 4 or 32, depending on the value of the PSCK bit. The prescaler divides this input by 1,
2, 4, or 8. Channels using TCR1 have the capability to resolve down to the TPU system clock divided
by 4.
TPUMCR — TPU Module Configuration Register
$YFFE00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP
TCR1P
TCR2P
EMU
T2CG
STF
SUPV
PSCK
0
IARB
RESET:
0
1
0
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