
MOTOROLA
MC68349 USER'S MANUAL
4- 27
4.3.2.4 RESET STATUS REGISTER (RSR). The RSR contains a bit for each reset source
to the SIM49. A set bit indicates the last type of reset that occurred, and only one bit can
be set in the register. The RSR is updated by the reset control logic when the SIM49
comes out of reset. This register can be read at any time; a write has no effect. For more
information, see Section 3 Bus Operation.
RSR
$007
76543210
EXT
POW
SW
DBF
0
LOC
SYS
0
Supervisor Only
EXT—External Reset
1 = The last reset was caused by an external signal driving RESET.
0 = The last reset was not caused by an external signal driving RESET.
POW—Power-Up Reset
1 = The last reset was caused by the power-up reset circuit.
0 = The last reset was not caused by the power-up reset circuit.
SW—Software Watchdog Reset
1 = The last reset was caused by the software watchdog circuit.
0 = The last reset was not caused by the software watchdog circuit.
DBF—Double Bus Fault Monitor Reset
1 = The last reset was caused by the double bus fault monitor.
0 = The last reset was not caused by the double bus fault monitor.
Bits 3, 0—Reserved by Motorola
LOC—Loss of Clock Reset
1 = The last reset was caused by a loss of frequency reference to the clock
synthesizer. This reset can only occur if the RSTEN bit in the SYNCR is set and
the VCO is enabled.
0 = The last reset was not caused by a loss of frequency reference to the clock
synthesizer.
SYS—System Reset
1 = The last reset was caused by the CPU32+ executing a RESET instruction. The
system reset does not load a reset vector or affect any internal CPU32+
registers, SIM49 configuration registers, or the MCR in each internal peripheral
module (DMA, quad data memory, and serial modules). It will, however, reset
external devices and all other registers in the peripheral modules.
0 = The last reset was not caused by the CPU32+ executing a RESET instruction.