參數(shù)資料
型號(hào)： MC68EC000
廠商： Motorola, Inc.
英文描述： Addendum to M68000 User Manual
中文描述： 增編M68000用戶手冊(cè)
文件頁(yè)數(shù)： 13/26頁(yè)
文件大?。?/td> 249K
代理商： MC68EC000
13
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued)
Applies to 3.3V and 5V.
NOTES:
1.
For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
2.
Actual value depends on clock period.
3.
If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
4.
For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the
system is powered up, #56 refers to the minimum pulse width required to reset the controller.
5.
If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
±
20%), subtract 5 ns from the values given in these columns.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
6.
When AS and R/W are equally loaded (
7.
NUM
CHARACTERISTIC
10MHz
MIN
0
—
0
—
16MHz
MIN
0
—
0
—
20MHz
MIN
0
—
0
—
UNIT
MAX
—
150
—
65
MAX
—
90
—
50
MAX
—
75
—
42
29
29A
30
2,5
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
AS, LDS, UDS Negated to Data-In High Impedance (Read)
AS, LDS, UDS Negated to BERR Negated
DTACK Asserted to Data-In Valid (Setup Time on Read)
ns
ns
ns
ns
31
32
33
34
35
HALT and RESET Input Transition Time
Clock High to BG Asserted
Clock High to BG Negated
BR Asserted to BG Asserted
BR Negated to BG Negated
0
—
—
1.5
1.5
150
35
35
3.5
3.5
0
—
—
1.5
1.5
150
30
30
3.5
3.5
0
—
—
1.5
1.5
150
25
25
3.5
3.5
ns
ns
ns
Clks
Clks
36
38
7
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
BG Width Negated
AS, LDS, UDS Negated to AVEC Negated
Asynchronous Input Setup Time
—
55
—
50
—
42
ns
39
44
1.5
0
5
—
55
—
1.5
0
5
—
50
—
1.5
0
5
—
42
—
Clks
ns
ns
47
5
48
2,3
BERR Asserted to DTACK Asserted
20
—
10
—
10
—
ns
52
53
55
Data-In Hold from Clock High
Data-Out Hold from Clock High (Write)
R/W Asserted to Data Bus Impedance Change (Write)
HALT, RESET Pulse Width
0
0
20
10
—
—
—
—
0
0
10
10
—
—
—
—
0
0
0
—
—
—
—
ns
ns
ns
Clks
56
4
10
58
7
BR Negated to AS, LDS, UDS, R/W Driven
1.5
—
1.5
—
1.5
—
Clks
58A
7
BR Negated to FC Driven
1
—
1
—
1
—
Clks
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