參數(shù)資料
型號(hào)： MC68EC030FE25C
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 12/36頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32 BIT ENHANCED 132-CQFP
標(biāo)準(zhǔn)包裝： 36
系列： M680x0
處理器類型： M680x0 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 132-BCQFP
供應(yīng)商設(shè)備封裝： 132-CQFP（24x24）
包裝： 托盤
2
MC68EC030 TECHNICAL DATA
MOTOROLA
INTRODUCTION
The MC68EC030 is an integrated controller that incorporates the capabilities of the MC68030 integer
unit, a data cache, an instruction cache, an access control unit (ACU), and an improved bus controller on
one VLSI device. It maintains the 32-bit registers available with the entire M68000 Family as well as the
32-bit address and data paths, rich instruction set, versatile addressing modes, and flexible coprocessor
interface provided with the MC68020 and MC68030. In addition, the internal operations of this integrated
controller are designed to operate in parallel, allowing instruction execution to proceed in parallel with
accesses to the internal caches and the bus controller.
The MC68EC030 fully supports the nonmultiplexed asynchronous bus of the MC68020 and MC68030
as well as the dynamic bus sizing mechanism that allows the controller to transfer operands to or from
external devices while automatically determining device port size on a cycle-by-cycle basis. In addition to
the asynchronous bus, the MC68EC030 also supports the fast synchronous bus of the MC68030 for off-
chip caches and fast memories. Like the MC68030, the MC68EC030 bus is capable of fetching up to four
long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst mode can
reduce (up to 50 percent) the time necessary to fetch the four long words. The four long words are used
to prefill the on-chip instruction and data caches so that the hit ratio of the caches is improved and the
average access time for operand fetches is minimized.
The MC68EC030 is specifically designed to sustain high performance while using low-cost (DRAM)
memory subsystems.
Coupled with the MC88916 clock generation and distribution circuit, the
MC68EC030 provides simple interface to lower speed memory subsystems. The MC88916 (see Figure
1) provides the precise clock signals required to efficiently control memory subsystems, eliminating
system design constraints due to clock generation and distribution.
MC68EC030
(40 MHz)
MC88916
20 MHz
OSC.
CONTROLLER
CLOCK (40 MHz)
BUS CLOCK
(40 MHz)
BUS CLOCK
(80 MHz)
3
BUS CLOCK
(20 MHz)
Figure 1.
MC68EC030 Clock Circuitry
The block diagram shown in Figure 2 depicts the major sections of the MC68EC030 and illustrates the
autonomous nature of these blocks. The bus controller consists of the address and data pads, the
multiplexers required to support dynamic bus sizing, and a microbus controller that schedules the bus
cycles on the basis of priority. The micromachine contains the execution unit and all related control logic.
Microcode control is provided by a modified two-level store of microROM and nanoROM contained in the
micromachine. Programmed logic arrays (PLAs) are used to provide instruction decode and sequencing
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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參數(shù)描述
MC68EC030FE25CB1 功能描述:IC MPU 32BIT ENH 25MHZ 132-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤
MC68EC030FE40B 制造商:Motorola Inc 功能描述:
MC68EC030FE40C 功能描述:微處理器 - MPU 32B ON-CHIP CACHE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68EC030FE40C 制造商:Freescale Semiconductor 功能描述:Microprocessor
MC68EC030RP25B 制造商:Motorola Inc 功能描述:68EC030RP25B
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