Signal Descriptions
MOTOROLA
MC68360 USER’S MANUAL
2-15
2.3 ON-CHIP PERIPHERALS SIGNAL INDEX
The input and output system signals for the QUICC peripherals are listed in Table 2-8. The
signal name, mnemonic, and a brief functional description are presented. For more detail on
each signal, refer to the specific module section. The peripherals pins are divided into three
ports: A, B, and C.
Port A has 16 pins, port B has 18 pins, and port C has 12 pins. All the following signals are
multiplexed with either port A, B, or C. All pins may be inputs or outputs; in addition, some
pins may be configured to be open-drain. See 7.14 Parallel I/O Ports for further details.
Table 2-7. System Bus Signal Index (Slave Mode) (Continued)
Master Mode
Mnemonic
Slave Mode
Signal Name
Slave Mode
Mnemonic
Slave Mode Function
PRTY0
Parity 0/Interrupt Out-
put 2
PRTY0/IOUT2ory bank (I/O), or interrupt output 2 signal (O).
PRTY1
Parity 1/Interrupt Out-
put 1
PRTY1/IOUT1ory bank (I/O) or interrupt output 1 signal. (O)
PRTY2
Parity 2/
Interrupt Output 0/
Request Output
PRTY2/IOUT0/
RQOUT
Parity signals for D15–D8 writes/reads from/to external memory
bank (I/O), or interrupt output 0 signal (O), or RQOUT as a sin-
gle interrupt request output (O).
AVEC/IACK5
Autovector Output
AVECO
Signal output to the external processor to generate an internal
vector number during an interrupt acknowledge cycle. (three-
stated O)
IPIPE1/
RAS1DD
Bus Clear Input/
Row Address Select 1
Double-Drive
BCLRI/
RAS1DD
Signals that an external device requests the QUICC to release
the external bus (I), or row address select 1 double-drive (O).
Table 2-8. Peripherals Signal Index
Group
Signal Name
Mnemonic
Function
SCC
Receive Data
RXD4–RXD1
Serial receive data input to the SCCs. (I)
Transmit Data
TXD4–TXD1
Serial transmit data output from the SCCs. (O)
Request to Send
RTS4–RTS1
Request to send outputs indicate that the SCC is ready to transmit
data. (O)
Clear to Send
CTS4–CTS1
Clear to send inputs indicate to the SCC that data transmission may
begin. (I)
Carrier Detect
CD4–CD1
Carrier detect inputs indicate that the SCC should begin reception of
data. (I)
Receive Start
RSTRT1
This output from SCC1 identifies the start of a receive frame. Can be
used by an Ethernet CAM to perform address matching. (O)
Receive Reject
RRJCT1
This input to SCC1 allows a CAM to reject the current Ethernet frame
after it determines the frame address did not match. (I)
Clocks
CLK8–CLK1
Input clocks to the SCCs, SMCs, SI, and the baud rate generators. (I)
IDMA
DMA Request
DREQ2–DREQ1
A request (input) to an IDMA channel to start an IDMA transfer. (I)
DMA Acknowledge
DACK2–DACK1
An acknowledgement (output) by the IDMA that an IDMA transfer is
in progress. (O)
DMA Done
DONE2–DONE1 of data. (I/O)
TIMER
Timer Gate
TGATE2–TGATE1 An input to a timer that enables/disables the counting function. (I)
Timer Input
TIN4–TIN1
Time reference input to the timer that allows it to function as a
counter. (I)