5- 20
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
BUS THREE-STATED
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED
BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE
BGACK NEGATED INTERNAL
BGACK SAMPLED
BGACK NEGATED
BR
BG
BGACK
AS
UDS
LDS
R/W
DTACK
D15–D0
PROCESSOR
ALTERNATE BUS MASTER
PROCESSOR
S0
S2
S4
S6
S0
S2
S4
S6
S0
CLK
FC2–FC0
A23–A1
Figure 5-21. 3-Wire Bus Arbitration Timing Diagram—Special Case
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Freescale Semiconductor, Inc.
For More Information On This Product,
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