參數(shù)資料
型號(hào)： MC68HC05BD3
廠商： Motorola, Inc.
英文描述： 8-Bit Microcontroller Units (MCU).(8位微控制器)
中文描述： 8位微控制器單元（MCU）。（8位微控制器）
文件頁(yè)數(shù)： 68/112頁(yè)
文件大?。?/td> 676K
代理商： MC68HC05BD3
MOTOROLA
8-8
MC68HC05BD3
SYNC SIGNAL PROCESSOR
8
SOUT - Sync Output Select
1 (set)
–
Use processed VSYNC and HSYNC inputs for VTTL and HTTL.
0 (clear) –
Use internally generated sync signals for VTTL and HTTL.
When cleared, the outputs to VTTL and HTTL are the internally generated signals. When set, the
outputs are the processed input signals. This bit can only be set if both VDET and HDET are logic
1’s, and will be cleared automatically if VDET or HDET is not logic “1”. Reset clears this bit.
INSRTB - Hsync Insertion Bit
1 (set)
–
No inserted pulses. Hsync remains high state during the vertical sync
pulse.
0 (clear) –
For composite sync inputs, emulated sync pulses will be inserted into
the Hsync signal during the vertical sync pulse.
For separate sync inputs, when this Hsync Insertion bit is cleared, sync pulses will continue to be
the Hsync signal during the Vertical Sync Pulse. For composite sync input, when this Hsync
Insertion bit is cleared, emulated sync pulses will be inserted into the Hsync signal during the
Vertical Sync Pulse. In both cases, when this bit is set, there will be no inserted pulses, and the
Hsync signal will be high during the Vertical Sync Pulse. Reset clears this bit.
FOUT - Internal Hsync Frequency Select
1 (set)
–
63.5Hz and 62.5KHz for VTTL and HTTL outputs respectively if
internally generated sync signals are selected.
0 (clear) –
63.5Hz and 48.8KHz for VTTL and HTTL outputs respectively if
internally generated sync signals are selected.
This bit selects the frequency of the free running Hsync signal to HTTL pin if SOUT bit is cleared.
When FOUT is set, 63.5Hz and 62.5KHz signals are output to VTTL and HTTL, respectively.
When FOUT is cleared, 63.5Hz and 48.8KHz signals are output instead. Reset clears this bits.
VSIN - Vsync Input Source
This bit selects the source of the input sync signals. Reset clears this bits.
1 (set)
–
Separated sync signals through VSYNC and HSYNC inputs.
0 (clear) –
Composite sync signal through HSYNC input
TPG
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