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參數(shù)資料
| 型號： | MC68HC05C8AMB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 55/116頁 |
| 文件大?。?/td> | 781K |
| 代理商： | MC68HC05C8AMB |
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Output Compare Register
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
43
8.3 Output Compare Register
The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17
(LSB). The output compare register is used for several purposes, such as indicating when a period of time
has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the
compare function is not needed, the two bytes of the output compare register can be used as storage
locations.
The output compare register contents are compared with the contents of the free-running counter
continually, and if a match is found, the corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) bit is clocked to an output level register. The output compare register
values and the output level bit should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt also can accompany a successful output compare, provided the
corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare register containing the MSB ($16), the output compare
function is inhibited until the LSB ($17) is written also. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The
free-running counter is updated every four internal bus clock cycles. The minimum time required to update
the output compare register is a function of the program rather than the internal hardware.
The processor can write to either byte of the output compare register without affecting the other byte. The
output level (OLVL) bit is clocked to the output level register regardless of whether the output compare
flag (OCF) is set or clear. Figure 8-2 shows the logic of the output compare function.
Figure 8-2. Output Compare Operation
16-BIT COMPARATOR
OUTPUT COMPARE REGISTER HIGH OUTPUT COMPARE REGISTER LOW
COUNTER HIGH BYTE
TCMP
PIN
CONTROL
LOGIC
TIMER
INTERRUPT
REQUEST
COUNTER LOW BYTE
15
0
15
8 7
0
TIMER STATUS REGISTER
$0013
TIMER CONTROL REGISTER
$0012
ICI
E
OCIE
TO
IE
ICF
OCF
TO
F
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