參數(shù)資料
型號: MC68HC05C9ACB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝: SHRINK, PLASTIC, DIP-42
文件頁數(shù): 37/160頁
文件大?。?/td> 4128K
代理商: MC68HC05C9ACB
Electrical Specifications
Serial Peripheral Interface Timing
MC68HC05C9A Rev. 4.0
General Release Specification
Electrical Specifications
NON-DISCLOSURE
AGREEMENT
REQUIRED
12.8 Serial Peripheral Interface Timing
Table 12-5. Serial Peripheral Interface Timing (V
DD = 5.0 Vdc)*
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f
OP
(M)
f
OP
(S)
dc
0.5
2.1
f
OP
MHz
1
Cycle Time
Master
Slave
t
CYC
(M)
t
CYC
(S)
2.0
480
t
CYC
ns
2
Enable Lead Time
Master
Slave
t
LEAD
(M)
t
LEAD
(S)
240
ns
3
Enable Lag Time
Master
Slave
t
LAG
(M)
t
LAG
(S)
720
ns
4
Clock (SCK) High Time
Master
Slave
t
W
(SCKH)M
t
W
(SCKH)S
340
190
ns
5
Clock (SCK) Low Time
Master
Slave
t
W
(SCKL)M
t
W
(SCKL)S
340
190
ns
6
Data Setup Time (Inputs)
Master
Slave
t
SU
(M)
t
SU
(S)
100
ns
7
Data Hold Time (Inputs)
Master
Slave
t
H
(M)
t
H
(S)
100
ns
8
Slave Access Time (Time to Data Active from
High-Impedance State)
t
A
0
120
ns
9
Slave Disable Time (Hold Time to High-Impedance State)
t
DIS
240
ns
10
Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)
t
V
(M)
t
V
(S)
0.25
240
t
CYC
(M)
ns
11
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
t
HO
(M)
t
HO
(S)
0.25
0
t
CYC
(M)
ns
12
Rise Time (20% V
DD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
t
RM
t
RS
100
2.0
ns
s
13
Fall Time (70% V
DD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
t
FM
t
FS
100
2.0
ns
s
NOTES:
*V
DD = 5.0 Vdc ± 10%; VSS = 0 Vdc, TA = –40 to +85 °C, unless otherwise noted. Refer to Figure 12-7 and Figure 12-8 for
timing diagrams.
Signal production depends on software.
Assumes 200 pF load on all SPI pins
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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