參數(shù)資料
型號(hào)： MC68HC05E1CDW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 59/86頁(yè)
文件大小： 709K
代理商： MC68HC05E1CDW
General Release Specication
MC68HC05E1 — Revision 2.0
62
Timer, Phase-Locked Loop, and Custom Periodic Interrupt
MOTOROLA
Timer, Phase-Locked Loop, and Custom Periodic
Example:
CLEARING TIMER OVERFLOW FLAG (TOF) BIT
SEI
SEI NOT REQUIRED IF USED WITHIN
TIMER INTERRUPT ROUTINE.
LDA
#$73
AND
$TCSR
OR
#$40
MASK RTIF BIT
STA
$TCSR
CLI
DO NOT USE CLI IF THIS CODE
SEGMENT IF USED WITHIN TIMER
INTERRUPT ROUTINE
CLEARING TIMER OVERFLOW ENABLE (TOFE) BIT
SEI
LDA
#$D3
AND
$TCSR
OR
#$C0
MASK RTIF & TOF
STA
$TCSR
CLI
DO NOT USE CLI IF THIS CODE
SEGMENT IF USED WITHIN TIMER
INTERRUPT ROUTINE
6.3.2 Computer Operating Properly (COP) Watchdog Reset
The COP watchdog timer function is implemented on this device by
using the output of the RTI circuit and further dividing it by eight. The
minimum COP reset rates are listed in Table 6-2. If the COP circuit times
out, an internal reset is generated and the normal reset vector is fetched.
Preventing a COP time-out is done by writing a ’0’ to bit 0 of address
$1FF0. When the COP is cleared, only the final divide by eight stage
(output of the RTI) is cleared.
This function is a mask option.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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