參數(shù)資料
型號: MC68HC05E1DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 37/86頁
文件大小: 709K
代理商: MC68HC05E1DW
General Release Specication
MC68HC05E1 — Revision 2.0
42
CPU Core
MOTOROLA
CPU Core
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-bit
state.
3.7.1 Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT) are not in the
strictest sense an interrupt; however, they are acted upon in a similar
manner. See Figure 3-1 and Figure 3-2. A discussion is provided below.
1. RESET - A low input on the RESET input pin causes the program
to vector to its starting address which is specified by the contents
of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset as previously described in
2. STOP - The STOP instruction causes the oscillator to be turned
off and the processor to “sleep” until an external interrupt (IRQ) or
reset occurs.
3. WAIT - The WAIT instruction causes all processor clocks to stop,
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ), or
Timer interrupt. There are no special wait vectors for these
individual interrupts.
Table 3-1. Vector Address for Interrupts and Reset
Register
Flag
Name
Interrupts
CPU
Interrupt
Vector Address
N/A
Reset
RESET
$1FFE–$1FFF
N/A
Software
SWI
$1FFC–$1FFD
N/A
External Interrupt
RQ
$1FFA–$1FFB
TCSR
TOF
Timer Overow
TIMER
$1FF8–$1FF9
RTIF
Real Time Interrupt
IMER
$1FF8–$1FF9
CPICSR
CPIF
Custom Periodic Interrupt
CPI
$1FF6–$1FF7
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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