參數(shù)資料
型號: MC68HC05E6CDW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 93/140頁
文件大小: 1584K
代理商: MC68HC05E6CDW
Programmable Timer
MC68HC05E6 — Rev. 1.0
Programmable Timer
TOIE — Timer overflow interrupt enable
1 = Timer overflow interrupt enabled.
0 = Timer overflow interrupt disabled.
IEDG — Input edge
1 = TCAP is positive-going edge sensitive.
0 = TCAP is negative-going edge sensitive.
When IEDG is set, a positive-going edge on the TCAP pin will trigger
a transfer of the free-running counter value to the input capture
register. When clear, a negative-going edge triggers the transfer.
OLV — Output level
1 = A high output level will appear on the TCMP pin.
0 = A low output level will appear on the TCMP pin.
When OLV is set, a high output level will be clocked into the output
level register by the next successful output compare, and will appear
on the TCMP pin. When clear, it will be a low level that will appear on
the TCMP pin.
Timer status
register TSR
The timer status register at location ($13) contains the status bits for the
input capture, output compare and timer overflow interrupt conditions.
Accessing the timer status register satisfies the first condition required
to clear the status bits. The remaining step is to access the register
corresponding to the status bit.
ICF — Input capture flag
1 = A valid input capture has occurred.
0 = No input capture has occurred.
This bit is set when the selected polarity of edge is detected by the
input capture edge detector; an input capture interrupt will be
generated if ICIE is set. ICF is cleared by reading the TSR and then
the input capture low register at $15.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer status (TSR)
$0013
ICF
OCF
TOF
00000
uuu0 0000
6-ptimer
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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