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參數(shù)資料
| 型號(hào)： | MC68HC05E6FB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 118/140頁(yè) |
| 文件大小： | 1584K |
| 代理商： | MC68HC05E6FB |
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Resets and Interrupts
Maskable hardware interrupts
MC68HC05E6 — Rev. 1.0
Resets and Interrupts
7-resets
To make use of the core timer overflow interrupt, the CTOFE bit must
first be set. The CTOF bit will then be set when the core timer counter
register overflows from $FF to $00.
Low voltage
indicator interrupt
The low voltage indicator on the MC68HC05E6 can be configured to
respond to a drop in supply voltage in two different ways: it can be
serviced by the user software or it can be set up to automatically
generate a system interrupt.
In both cases, the power supply could be connected to a low voltage
detection circuit which is in turn connected to the LVI pin of the device.
This allows the voltage from the power supply to be monitored and, if the
voltage being supplied to the device falls below a useful operating
voltage, the LVI pin will be driven low and the LVIVAL bit in the
LVI/options register (LVIOPT) will be cleared.
It is at this point that the user can decide which way the system should
respond. The first method is one in which the user program continually
checks the LVIVAL bit for a ‘0’, at which point it enters a particular routine
whereby all useful information is saved and the device enters a
predefined operating state, e.g. WAIT or STOP mode.
The second method is one whereby a ‘0’ in the LVIVAL bit of LVIOPT
automatically generates a system interrupt, provided LVIE is set. The
occurrence of a valid LVI interrupt can be detected by reading the
LVIINT bit of the LVI/options register. The LVI interrupt has a dedicated
vector at $1FF6–$1FF7.
NOTE:
The interrupt service routine must reset the interrupt by writing a ‘1’ to
the LVIRST bit in LVIOPT.
The main feature of these methods of LVI handling is that the user can
shut down the micro and the application in an orderly manner before the
voltage drops below a useful operating voltage.
If the CPU performs a power-on reset due to a supply voltage below the
power-on trip level, no interrupt will be performed and the CPU start-up
will be delayed until LVI becomes high (see Figure 20).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05E6MDW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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