參數(shù)資料
型號(hào): MC68HC05E6MDWR2
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁(yè)數(shù): 115/140頁(yè)
文件大小: 1141K
代理商: MC68HC05E6MDWR2
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Resets and Interrupts
MC68HC05E6 — Rev. 1.0
76
Resets and Interrupts
MOTOROLA
providing the corresponding enable bit stored on the stack is zero, i.e.
the interrupt is disabled.
Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete. The current instruction is the one already fetched
and being operated on. When the current instruction is complete, the
processor checks all pending hardware interrupts. If interrupts are not
masked (CCR I-bit clear) and the corresponding interrupt enable bit is
set, the processor proceeds with interrupt processing; otherwise, the
next instruction is fetched and executed.
NOTE:
Power-on or external reset clear all interrupt enable bits thus preventing
interrupts during the reset sequence.
Interrupt priorities
Each potential interrupt source is assigned a priority which means that if
more than one interrupt is pending at the same time, the processor will
service the one with the highest priority first. For example, if both an
external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
Table 11 shows the relative priorities of all the possible interrupt
sources. Figure 19 shows the interrupt processing flow.
Table 11 Interrupt priorities
Source
Register
Flags
Vector address
Priority
Reset
$1FFE, $1FFF
highest
Software interrupt (SWI)
$1FFC, $1FFD
External interrupt (IRQ)
$1FFA, $1FFB
Core timer
CTCSR
CTOF, RTIF
$1FF8, $1FF9
Low voltage interrupt
LVIOPT
LVIINT
$1FF6–$1FF7
16-bit timer
TSR
ICF, OCF, TOF
$1FF4, $1FF5
Keyboard interrupt
KEY/TIM
KSF
$1FF2, $1FF3
4-resets
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