參數(shù)資料
型號: MC68HC05J1AVDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝: SOIC-20
文件頁數(shù): 90/126頁
文件大?。?/td> 1118K
代理商: MC68HC05J1AVDWR2
Technical Data
MC68HC05J1A — Rev. 1.0
66
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
7.5.2 Data Direction Register B
The contents of data direction register B (DDRB) determine whether
each port B pin is an input or an output. Writing a logic 1 to a DDRB bit
enables the output buffer for the associated port B pin; a logic 0 disables
the output buffer. A reset initializes all DDRB bits to logic 0, configuring
all port B pins as inputs.
DDRB5–DDRB0 — Data Direction Bits
These read/write bits control port B data direction.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Bit 7 and 6 — Not used
Bits 7 and 6 always read as logic 0s. Writes to these bits have no
effect.
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
Address:
$0005
Bit 7
654321
Bit 0
Read:
0
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
Write:
Reset:
00000000
= Unimplemented
Figure 7-6. Data Direction Register B (DDRB)
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