參數(shù)資料
型號(hào): MC68HC05J3CDW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝: PLASTIC, SOIC-20
文件頁(yè)數(shù): 27/92頁(yè)
文件大?。?/td> 912K
代理商: MC68HC05J3CDW
MC68HC05J3
MOTOROLA
4-5
INPUT/OUTPUT PORTS
4
KIE — Keyboard interrupt enable
1 (set)
Keyboard interrupt enabled on port B.
0 (clear) –
Keyboard interrupt disabled.
TCAP — Timer input capture function
1 (set)
PB5 acts as the TCAP input to the 16-bit timer. The pin is forced to
an input state regardless of the data direction bit.
0 (clear) –
PB5 functions as a normal I/O pin.
TCMP — Timer output compare function
1 (set)
PB4 acts as the TCMP output for the 16-bit timer. The pin is forced to
an output state regardless of the data direction bit.
0 (clear) –
PB4 functions as a normal I/O pin.
Bits 3–0 are not implemented on the conguration register and always read zero. Writing to these
bits has no meaning or effect.
4.4.4
Data direction register A (DDRA)
Writing a ‘1’ to any bit congures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ congures the corresponding port pin as an input.
Reset clears these registers, thus conguring all pins as inputs.
4.4.5
Data direction register B (DDRB)
Writing a ‘1’ to any bit congures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ congures the corresponding port pin as an input.
Reset clears these registers, thus conguring all pins as inputs.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port A data direction (DDRA)
$0004
0000 0000
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port B data direction (DDRB)
$0005
0
0000 0000
TPG
30
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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