參數(shù)資料
型號(hào): MC68HC05J3CP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁(yè)數(shù): 50/74頁(yè)
文件大?。?/td> 814K
代理商: MC68HC05J3CP
MOTOROLA
7-4
MC68HC05J3
RESETS AND INTERRUPTS
7
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
Note:
Power-on or external reset clear all interrupt enable bits thus preventing interrupts
during the reset sequence.
7.3.1
Interrupt priorities
Each potential interrupt source is assigned a priority which means that if more than one interrupt
is pending at the same time, the processor will service the one with the highest priority rst. For
example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced rst.
Table 7-2 shows the relative priority of all the possible interrupt sources. Figure 7-2 shows
the interrupt processing ow.
Table 7-2 Interrupt priorities
Source
Register
Flags
Vector address
Priority
Reset
$0FFE, $0FFF
highest
Software interrupt (SWI)
$0FFC, $0FFD
External interrupt (IRQ)/
keyboard interrupt
CONFB
PTBIF
$0FFA, $0FFB
Core timer
CTCSR
CTOF, RTIF
$0FF8, $0FF9
16-bit timer – input capture
TSR
ICF
$0FF6, $1FF7
16-bit timer – output compare
TSR
OCF
$0FF4, $0FF5
16-bit timer – overow
TSR
TOF
$0FF2, $0FF3
Reserved
$0FF0, $0FF1
TPG
51
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