參數(shù)資料
型號(hào)： MC68HC05J5AJDWR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 65/106頁
文件大?。?/td> 1069K
代理商： MC68HC05J5AJDWR2
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
16-BIT TIMER
MOTOROLA
REV 2.1
9-3
The timer counter registers (TCNTH, TCNTL) shown in Figure 9-3 are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the timer registers has no effect. Reset of the device presets
the timer counter to $FFFC.
The TCNTL latch is a transparent read of the LSB until the a read of the TCNTH
takes place. A read of the TCNTH latches the LSB into the TCNTL location until
the TCNTL is again read. The latched value remains xed even if multiple reads of
the TCNTH take place before the next read of the TCNTL. Therefore, when read-
ing the MSB of the timer at TCNTH the LSB of the timer at TCNTL must also be
read to complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is 16 bits and pre-
ceded by a xed divide-by-four prescaler, the value in the counter repeats every
262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer overow
ag bit (T1OF) is set in the T1SR. When the T1OF is set, it can generate an inter-
rupt if the timer overow interrupt enable bit (T1OIE) is also set in the T1CR. The
T1OF ag bit can only be reset by reading the TCNTL after reading the T1SR.
Other than clearing any possible T1OF ags, reading the TCNTH and TCNTL in
any order or any number of times does not have any effect on the 16-bit free-run-
ning counter.
NOTE
To prevent interrupts from occurring between readings of the TCNTH and TCNTL,
set the I bit in the condition code register (CCR) before reading TCNTH and clear
the I bit after reading TCNTL.
9.2
ALTERNATE COUNTER REGISTERS (ACNTH, ACNTL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in Figure 9-4. The alternate counter registers behave
the same as the timer counter registers, except that any reads of the alternate
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TCNTH
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
$0018
W
reset:
11111111
TCNTL
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0019
W
reset:
11111100
Figure 9-3. 16-Bit Timer Counter Registers (TCNTH, TCNTL)
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