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參數(shù)資料
| 型號： | MC68HC05J5DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 36/69頁 |
| 文件大小： | 394K |
| 代理商： | MC68HC05J5DW |
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December 11, 1996
GENERAL RELEASE SPECIFICATION
MC68HC05J5
INPUT/OUTPUT PORTS
MOTOROLA
REV 1.1
7-1
SECTION 7
INPUT/OUTPUT PORTS
In the Single-Chip Mode there are 14 usable bidirectional I/O lines arranged as
one 8-bit I/O port (Port A), and one 6-bit I/O port (Port B). The individual bits in
these ports are programmable as either inputs or outputs under software control
by the data direction registers (DDR’s). Also, if enabled by a single mask option all
Port A and Port B I/O pins may have individual software programmable pull-down
or pull-up devices. Also, PA4-PA7 and PB1-PB2 pins have properties of sinking
higher current; PA0-PA3 may function as additional IRQ interrupt input sources.
Note that both PA6 and PA7 pins have Schmitt trigger input for better noise
immunity. VIH and VIL specied at 2.4V and 0.8V, respectively.
7.1
SLOW OUTPUT FALLING-EDGE TRANSITION
Figure 7-1. Port B Data Direction Register
SLOWE - Slow Transition Enabled
The slow transition feature is controlled by the SLOWE bit of DDRB (Port B
Data Direction Register).
1 =
Enables the slow falling-edge output transition feature on the four
I/O lines: PA6, PA7, PB1, and PB2. If the pin is congured as an
output pin.
0 =
Disables slow falling-edge output transition feature on the four I/O
lines: PA6, PA7, PB1, and PB2. Default value of SLOWE bit is
cleared.
7.2
PORT A
Port A is an 8-bit bi-directional port which shares ve of its pins with the IRQ
interrupt system as shown in Figure 7-2. Note that both PA6 and PA7 pins have
Schmitt trigger input for better noise immunity. Only PA6 and PA7 are of open-
drained type with slow output transition feature. Each Port A pin is controlled by
0
DDRB0
DDRB
$0005
0
7
W
R
0000000
reset
6543210
SLOWE
DDRB1
DDRB2
DDRB3
DDRB4
DDRB5
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