參數(shù)資料
型號(hào): MC68HC05JB3JDW
廠(chǎng)商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁(yè)數(shù): 140/148頁(yè)
文件大?。?/td> 1600K
代理商: MC68HC05JB3JDW
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November 5, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05JB3
UNIVERSAL SERIAL BUS MODULE
MOTOROLA
REV 1
10-23
RX0E — Endpoint 0 Receive Enable
This read/write bit enables a receive to occur when the USB Host controller
sends an OUT token to Endpoint 0. Software should set this bit when data is
ready to be received. It must be cleared by software when data cannot be
received.
If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake
to any Endpoint 0 OUT tokens. Reset clears this bit.
1 =
Data is ready to be received.
0 =
Not ready for data. Respond with NAK.
TP0SIZ3-TP0SIZ0 — Endpoint 0 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the next IN
token request for Endpoint 0. These bits are cleared by reset.
10.5.5 USB Control Register 1 (UCR1)
T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or DATA1) will
be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.
Toggling of this bit must be controlled by software. Reset clears this bit.
1 =
DATA1 Token active for next Endpoint 1/Endpoint 2 transmit.
0 =
DATA0 Token active for next Endpoint 1/Endpoint 2 transmit.
ENDADD — Endpoint Address Select
This
read/write
bit
species
whether
the
data
inside
the
registers
UE1D0-UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for a
successful Endpoint 2 USB response to a hosts IN token are satised
(TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bit
is congured for Endpoint 1, the USB responds with a NAK handshake packet.
1 =
The data buffers are used for Endpoint 2.
0 =
The data buffers are used for Endpoint 1.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UCR1
R
T1SEQ
ENDADD
TX1E
FRESUM TP1SZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
$003C
W
reset:
00000000
Figure 10-24. USB Control Register 1 (UCR1)
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