參數(shù)資料
型號(hào): MC68HC05JJ6CP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁(yè)數(shù): 20/228頁(yè)
文件大?。?/td> 2138K
代理商: MC68HC05JJ6CP
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Analog Subsystem
General Release Specification
MC68HC05JJ6/MC68HC05JP6 Rev. 3.0
116
Analog Subsystem
MOTOROLA
CPFR2
Writing a logical one to this write-only flag clears the CPF2 flag in the
ASR. Writing a logical zero to this bit has no effect. Reading the
CPFR2 bit will return a logical zero. By default, this bit looks cleared
following a reset of the device.
1 = Clears the CPF2 flag bit
0 = No effect
CPFR1
Writing a logical one to this write-only flag clears the CPF1 flag in the
ASR. Writing a logical zero to this bit has no effect. Reading the
CPFR1 bit will return a logical zero. By default, this bit looks cleared
after a reset of the device.
1 = Clears the CPF1 flag bit
0 = No effect
NOTE:
The CPFR1 and CPFR2 bits should be written with logical ones following
a power up of either comparator. This will clear out any latched CPF1 or
CPF2 flag bits which might have been set during the slower power up
sequence of the analog circuitry.
If both inputs to a comparator are above the maximum common-mode
input voltage (VDD–1.5 V) the output of the comparator is indeterminate
and may set the comparator flag. Applying a reset to the device may only
temporarily clear this flag as long as both inputs of a comparator remain
above the maximum common-mode input voltages.
VOFF
This read-write bit controls the addition of an offset voltage to the
bottom of the sample capacitor. It is not active unless selected by a
mask option. Any reads of the VOFF bit location return a logical zero
if the analog options’ mask option is disabled. During the time that the
sample capacitor is connected to an input (either HOLD or DHOLD
set), the bottom of the sample capacitor is connected to VSS. The
VOFF bit is cleared by a reset of the device.
1 = Enable approximately 100-mV offset to be added to the sample
voltage when both the HOLD and DHOLD control bits are
cleared.
0 = Connect the bottom of the sample capacitor to VSS.
相關(guān)PDF資料
PDF描述
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