參數(shù)資料
型號: MC68HC05K0P
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 119/154頁
文件大?。?/td> 1585K
代理商: MC68HC05K0P
Parallel Input/Output (I/O)
Port A
MC68HC05K0 MC68HC05K1 — Rev. 2.0
Technical Data
Parallel Input/Output (I/O)
7.3.2 Data Direction Register A
The contents of data direction register A (DDRA), shown in Figure 7-2,
determine whether each port A pin is an input or an output. Writing a
logic 1 to a DDRA bit enables the output buffer for the associated port A
pin; a logic 0 disables the output buffer. A reset initializes all DDRA bits
to logic 0s, configuring all port A pins as inputs. If the pulldown devices
are enabled by mask option, setting a DDRA bit to a logic 1 turns off the
pulldown device for that pin.
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears bits
DDRA7–DDRA0.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
Address:
$0004
Bit 7
654321
Bit 0
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
00000000
Figure 7-2. Data Direction Register A (DDRA)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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