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參數(shù)資料
| 型號： | MC68HC05K3CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 118/132頁 |
| 文件大?。?/td> | 2612K |
| 代理商： | MC68HC05K3CDW |
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Technical Data
MC68HC05K3 — Rev. 5
Personality EEPROM (PEEPROM)
Personality EEPROM (PEEPROM)
The programming of a PEEPROM bit only requires access of that bit
through the PEBSR followed by setting the PEPGM and CPEN bits in the
PESCR. Do not access any bits that are to be left unprogrammed
(erased) until all the PEPGM, PEBYTE, PEBULK, and CPEN bits in the
PESCR are cleared. Always clear the PEPGM, PEBYTE, PEBULK, and
CPEN bits before altering the PEBSR.
9.5 PEEPROM Read Access
The contents of the PEEPROM are read in this sequence:
1. Write the desired bit location to be read into the PEBSR located at
$000E.
2. Read the state of the PEDATA bit in the PESCR located at $000F.
3. Store the state of the PEDATA bit into RAM or a register.
4. Select another bit by changing the PEBSR.
5. Continue reading and storing the PEDATA bit states until all the
required PEEPROM data has been accessed.
Reading the PEEPROM is easiest when each row in the PEEPROM
array is mapped to contain one byte of data. Selecting a column zero bit
selects the first bit in the row; and incrementing the PEEPROM bit select
register (PEBSR) selects the next (column 1) bit from the same row.
Incrementing the PEBSR seven more times selects the remaining bits of
the row and carries over to select column zero of the next row, thereby
setting the column zero flag, PEPCZF in the PESCR. The number of
increments per row can be controlled by looping on a test of the PEPCZF
flag bit.
The complete array can be easily accessed by starting with $007F for
the PEBSR and decrementing the PEBSR after each access of the
PEDATA bit. The decrement sequence can end when the contents of the
PEBSR are 0.
NOTE:
One byte of data from the PEEPROM can be re-created in the PEBSR
itself. This can be done if the read routine builds the 8-bit data byte in the
index register or the accumulator and then transfers that result to the
PEBSR when completed. Subsequent reads of the PEBSR quickly yield
that retrieved data byte.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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ARCHIVED
BY
FREESCALE
SEMICONDUCT
OR,
INC.
2006
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| MC68HC05K3CSDR2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO20 |
| MC68HC05K3CDWR2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05K3CP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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| MC68HC05K3DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05K3P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05L10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcomputer Unit |
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