參數(shù)資料
型號: MC68HC05P18MDWR3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 141/144頁
文件大?。?/td> 1348K
代理商: MC68HC05P18MDWR3
Advance Information
MC68HC(8)05P18 — Rev. 2.0
96
16-Bit Timer
MOTOROLA
16-Bit Timer
the application software, a timer interrupt flag (TOF) could
unintentionally be cleared if:
1. The TSR is read when bit 5 (TOF) is set.
2. The LSB of the free-running counter is read, but not for the
purpose of servicing the flag or interrupt.
The alternate counter registers (ACRH and ACRL) contain the same
values as the timer registers (TMRH and TMRL). Registers ACRH and
ACRL can be read at any time without affecting the timer overflow flag
(TOF) or interrupt.
ICF — Input Capture Flag
Bit 7 is set when the edge specified by IEDG in register TCR has been
sensed by the input capture edge detector fed by pin TCAP. This flag
and the input capture interrupt can be cleared by reading register TSR
followed by reading the LSB of the input capture register pair (ICRL).
OCF — Output Compare Flag
Bit 6 is set when the contents of the output compare registers match
the contents of the free-running counter. This flag and the output
compare interrupt can be cleared by reading register TSR followed by
writing the LSB of the output compare register pair (OCRL).
TOF — Timer Overflow Flag
Bit 5 is set by a rollover of the free-running counter from $FFFF to
$0000. This flag and the timer overflow interrupt can be cleared by
reading register TSR followed by reading the LSB of the timer register
pair (TMRL).
Address:
$0013
Bit 7
654321
Bit 0
Read:
ICF
OCF
TOF
00000
Write:
Reset:
U
00000
= Unimplemented
U = Unaffected
Figure 10-11. Timer Status Register (TSR)
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