參數(shù)資料
型號(hào)： MC68HC05P4A
廠商： Motorola, Inc.
英文描述： 28-pin MCU (microcontroller unit) based on the MC68HC05P4(28引腳、基于MC68HC05P4升級(jí)的8位微控制器單元)
中文描述： 28引腳單片機(jī)（微控制器）的基礎(chǔ)上MC68HC05P4（28引腳，基于MC68HC05P4升級(jí)的8位微控制器單元）
文件頁(yè)數(shù)： 54/102頁(yè)
文件大小： 930K
代理商： MC68HC05P4A
Advance Information
MC68HC05P4A — Rev. 6.0
54
Simple Serial Input/Output Port (SIOP)
MOTOROLA
Simple Serial Input/Output Port (SIOP)
7.4 SIOP Registers
The SIOP registers are described here.
7.4.1 SIOP Control Register
This register is located at address $000A and contains two bits.
SPE — Serial Peripheral Enable Bit
When set, this bit enables the serial I/O port and initializes the port B
DDR such that PB5 (SDO) is output, PB6 (SDI) is input, and PB7
(SCK) is input (slave mode only). The port B DDR can be altered
subsequently as the application requires and the port B data register
(except for PB5) can be manipulated as usual. However, these
actions could affect the transmitted or received data. When SPE is
cleared, port B reverts to standard parallel I/O without affecting the
port B data register or DDR. SPE is readable and writable any time
but clearing SPE while a transmission is in progress will abort the
transmission, reset the bit counter, and return port B to its normal I/O
function. Reset clears this bit.
MSTR — Master Mode Bit
When set, this bit configures the SIOP for master mode. This means
that the transmission is initiated by a write to the data register and the
SCK pin becomes an output providing a synchronous data clock at a
fixed rate of E (bus clock) divided by four. While the device is in
master mode, the SDO and SDI pins do not change function. These
pins behave exactly as they would in slave mode. Reset clears this
Address:
$000A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
SPE
0
MSTR
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-3. SIOP Control Register (SCR)
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