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參數(shù)資料
| 型號： | MC68HC05P9DWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 11/88頁 |
| 文件大?。?/td> | 6557K |
| 代理商： | MC68HC05P9DWR2 |
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2
MOTOROLA
2-4
MC68HC05E0
FUNCTIONAL PIN DESCRIPTION
2.7
Port D (PD0 - PD7)
Port D is comprised of eight bidirectional pins (PD0 to PD7). The direction and state of each pin
is software programmable. Alternatively, Port D can be congured to provide address and control
lines for interfacing to external memory. During power-on or reset all port pins except PD0 are
dened as port inputs: PD0 is dened as an output and generates the internal bus timing signal
P02.
2.8
Port E (PE0 - PE3)
Port E is comprised of four bidirectional pins (PE0 to PE3). The direction and state of each pin is
software programmable. In addition, Port E can be congured to support the SPI and I2C-bus
functions. All pins are congured as inputs during power-on or reset.
2.9
CSROM
This active low output signal is used as a chip select for external ROM. If the XROM bit in the Timer
Control Register ($000C) is set to 1, this pin outputs a logic zero when an address in the range
$3000 to $FFFF is present on the address bus. CSROM is normally gated with P02 and is only
active during the “high” phase of P02. However, writing a logic zero to the XROM bit in the Timer
Control Register ($000C) forces CSROM to remain permanently low throughout the full memory
map ($0000-$FFFF). Clearing the XROM bit also has the effect of making all data bus lines input
only. This feature is intended for use in a two chip system (MC68HC05E0 and ROM/EPROM) and
helps minimise the amount of RFI generated by rapid switching of the bus and CSROM lines.
Note:
Although CSROM is permanently low throughout the full memory map, data on the data
bus will be ignored between addresses $0000-$01FF. This space is reserved for
internal memory in the MC68HC05E0. (The XROM bit does not affect the internal
memory map and Read and Write instructions can be executed as normal in this area.)
XROM
CSROM Pin
Data Bus
1
gated P02 ($3000-$FFFF)
Input/Output
0
always 0 ($0000-$FFFF)
Input only
20
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