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參數(shù)資料
| 型號： | MC68HC05RC16P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 89/122頁 |
| 文件大?。?/td> | 2962K |
| 代理商： | MC68HC05RC16P |
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Carrier Modulator Transmitter (CMT)
Overview
MC68HC05RC16 — Rev. 3.0
General Release Specification
Carrier Modulator Transmitter (CMT)
Figure 9-1. Carrier Modulator Transmitter Module Block Diagram
The modulator provides a simple method to control protocol timing. The
modulator has a resolution of 4
s with a 2-MHz oscillator. It can count
system clocks to provide real-time control or it can count carrier clocks
for self-clocked protocols. It can either gate the carrier onto the
modulator output (TIME), control the logic level of the modulator output
(baseband) or directly route the carrier to the modulator output while
providing a signal to switch the carrier generator between high/low time
register buffers (FSK). See 9.5 Modulator.
The transmitter output block controls the state of the infrared out pin
(IRO). The modulator output is gated on to the IRO pin when the
modulator/carrier generator is enabled. Otherwise, the IRO pin is
controlled by the state of the IRO latch, which is directly accessible to the
CPU by means of bit 7 of the carrier generator data registers CHR1 and
CLR1. The IRO latch can be written to on either edge of the internal bus
clock (fosc/2), allowing for IR waveforms which have a resolution of twice
fOSC
CARRIER
GENERATOR
MODULATOR
CARRIER
OUT
MODULATOR
OUT
MODULATOR/
TRANSMITTER
OUTPUT
BASE
MODE
PRIMARY/SECONDARY SELECT
CPU INTERFACE
IRO
PIN
EOC
FLA
G
fOSC ÷ 2
DB
AB
EOC INTERRUPT
EOC
ENABLE
.
INTERR
UPT
CARRIER
ENABLE
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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