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參數(shù)資料
| 型號： | MC68HC05RC18DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 89/124頁 |
| 文件大?。?/td> | 457K |
| 代理商： | MC68HC05RC18DW |
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Core Timer
Core Timer Counter Register
MC68HC05RC18 — Rev. 2.0
General Release Specification
MOTOROLA
Core Timer
67
NON-DISCLOSURE
AGREEMENT
REQUIRED
8.4 Core Timer Counter Register
The timer counter register is a read-only register that contains the
current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked by the CPU clock (E/4) and can be used
for various functions, including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location, thereby simulating a 16-bit (or more) counter.
The power-on cycle and the low-power reset both serve to clear the
entire counter chain and begin clocking the counter. After 4064 cycles,
the power-on/low-power reset circuit is released, which again clears the
counter chain and allows the device to come out of reset. At this point, if
RESET is not asserted, the timer starts counting up from zero and
normal device operation begins. When a reset other than POR and low-
power reset is asserted any time during operation, the counter chain is
cleared but the 4064-cycle stabilization period is not invoked.
8.5 Computer Operating Properly (COP) Reset
The COP watchdog timer function is implemented on this device by
using the output of the RTI circuit and further dividing it by eight. The
minimum COP reset rates are listed in Figure 8-1. If the COP circuit
times out, an internal reset is generated and the normal reset vector is
fetched. Preventing a COP timeout, or clearing the COP is accomplished
by writing a zero to bit 0 of address $3FF0. When the COP is cleared,
only the final divide-by-eight stage (output of the RTI) is cleared.
Address
$0009
Bit 7
654321
Bit 0
Read:
D7
D6
D5
D4
D3
D2
D1
D0
Write:
Reset:
00000000
= Unimplemented
Figure 8-3. Timer Counter Register (CTCR)
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