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參數(shù)資料
| 型號： | MC68HC05RC18P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 102/126頁 |
| 文件大?。?/td> | 1180K |
| 代理商： | MC68HC05RC18P |
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Carrier Modulator Transmitter (CMT)
MC68HC05RC18 — Rev. 2.1
General Release Specification
Freescale Semiconductor
Carrier Modulator Transmitter (CMT)
75
NON-DISCLOSURE
AGREEMENT
REQUIRED
PH0–PH5 and PL0–PL5 — Primary Carrier High
and Low Time Data Values
When selected, these bits contain the number of input clocks required
to generate the carrier high and low time periods. When operating in
time mode (see 9.5.1 Time Mode), this register pair is always
selected. When operating in FSK mode (see 9.5.2 FSK Mode), this
register pair and the secondary register pair are alternately selected
under control of the modulator. The primary carrier high and low time
values are undefined out of reset. These bits must be written to
nonzero values before the carrier generator is enabled to avoid
spurious results.
NOTE:
Writing to CHR1 to update PH0–PH5 or to CLR1 to update PL0–PL5 will
also update the IRO latch. When MCGEN (bit 0 in the MCSR) is clear,
the IRO latch value appears on the IRO output pin. Care should be taken
that bit 7 of the data to be written to CHR1 or CHL1 should contain the
desired state of the IRO latch.
Additionally, writing to CHR1 to update PH0–PH5 will also update the
CMT polarity bit. Care should be taken that bit 6 of the data to be written
to CHR1 should contain the desired state of the polarity bit.
SH0–SH5 and SL0–SL5 — Secondary Carrier High
and Low Time Data Values
When selected, these bits contain the number of input clocks required
to generate the carrier high and low time periods. When operating in
time mode (see 9.5.1 Time Mode), this register pair is never selected.
When operating in FSK mode (see 9.5.2 FSK Mode), this register pair
and the primary register pair are alternately selected under control of
the modulator. The secondary carrier high and low time values are
undefined out of reset. These bits must be written to nonzero values
before the carrier generator is enabled when operating in FSK mode.
CMTPOL — CMT output Polarity
This bit controls the polarity of the CMT output (IRO). When this bit is
a zero, then the CMT output is active high. When this bit is set to one
the CMT output is active low, in other words inverted. The reset state
of this bit is zero.
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