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| 型號(hào)： | MC68HC05RC8FN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 102/122頁(yè) |
| 文件大?。?/td> | 2962K |
| 代理商： | MC68HC05RC8FN |
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Carrier Modulator Transmitter (CMT)
General Release Specification
MC68HC05RC16 — Rev. 3.0
Carrier Modulator Transmitter (CMT)
9.5.3.2 Modulator Control and Status Register
The modulator control and status register (MCSR) contains the
modulator and carrier generator enable (MCGEN), interrupt enable (IE),
mode select (MODE), baseband enable (BASE), extended space
(EXSPC), and external interrupt mask (EIMSK) control bits,
divide-by-two prescaler (DIV2) bit, and the end of cycle (EOC) status
bit.
EOC — End Of Cycle Status Flag
EOC is set when a match occurs between the contents of the space
period register, SREG, and the down counter. This is recognized as
the end of the modulation cycle. At this time, the counter is initialized
with the (possibly new) contents of the mark period buffer, MBUFF,
and the space period register, SREG, is loaded with the (possibly
new) contents of the space period buffer, SBUFF. This flag is cleared
by a read of the MCSR followed by an access of MDR2 or MDR3. The
EOC flag is cleared by reset.
1 = End of modulator cycle (counter = SBUFF) has occurred
0 = Current modulation cycle in progress
DIV2 — Divide-by-two prescaler
The divide-by-two prescaler causes the CMT to be clocked at the bus
rate when enabled; 2 x the bus rate when disabled (fosc). This bit is
not double buffered and so should not be set during a transmission.
1 = Divide-by-two prescaler enabled
0 = Divide-by-two prescaler disabled
Address:
$0014
Bit 7
654321
Bit 0
Read:
EOC
DIV2
EIMSK
EXSPC
BASE
MODE
IE
MCGEN
Write:
Reset:
00000000
Unimplemented
Figure 9-10. Modulator Control and Status Register (MCSR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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