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參數(shù)資料
| 型號(hào)： | MC68HC05SR3 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Units |
| 中文描述： | 高密度互補(bǔ)金屬氧化物半導(dǎo)體（HCMOS）微控制器單元 |
| 文件頁數(shù)： | 21/96頁 |
| 文件大?。?/td> | 3045K |
| 代理商： | MC68HC05SR3 |
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Freescale
3-2
MC68HC05SR3
INPUT/OUTPUT PORTS
3
3.1.2
Port Data Direction Registers
Each port pin may be programmed as an input by clearing the corresponding bit in the DDR, or
programmed as an output by setting the corresponding bit in the DDR. The DDR for Port A, B, C,
and D are located at $04, $05, $06 and, $07 respectively. The DDRs are cleared by reset.
Note:
A “glitch” may occur on an I/O pin when selecting from an input to an output unless the
data register is first preconditioned to the desired state before changing the
corresponding DDR bit from a “0” to a “1”.
3.2
Port A — Keyboard Interrupts (KBI)
Port A is configured for use as keyboard interrupts when the KBIE bit is set in the Miscellaneous
Control Register (MCR). Individual keyboard interrupt port pins are also maskable by setting
corresponding bits in the Keyboard Interrupt Mask Register.
See Section 5.2.2.4 for details on the keyboard interrupts.
3.3
PD0:PD5 — ADC Inputs
When the ADON bit is set in the ADC Status and Control Register, PD0 to PD3 are configured as
ADC inputs AN0 to AN3 respectively. PD4 and PD5 are configured as VRL and VRH respectively.
See Section 7 for details on the Analog to Digital Converter.
Figure 3-1 Port I/O Circuitry
INPUT
REGISTER
BIT
INPUT I/O
OUTPUT
I/O PIN
DATA DIRECTION
REGISTER BIT
LATCHED OUTPUT
DATA BIT
INTERNAL
MC68HC05
CONNECTIONS
TPG
26
05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM
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| MC68HC05SU3A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Fully static chip design featuring the industry standard 8-bit M68HC05 core |
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