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參數(shù)資料
| 型號(hào)： | MC68HC05SR3FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 90/96頁 |
| 文件大小： | 612K |
| 代理商： | MC68HC05SR3FB |
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MOTOROLA
A-4
MC68HC05SR3
MC68HC705SR3
A
CLR
PCR
;reset PCR
LDX
#$00
;load index register with 00
BSET
1,PCR
;set ELAT bit
LDA
#$00
;load data = 00 in to A
STA
$1900,X
;latch data and address
BSET
0,PCR
;program
JSR
DELAY
;call delay subroutine for 1ms
CLR
PCR
;reset PCR
A.5
Mask Option Register (MOR)
The Mask Option Register (MOR) contains programmable EPROM bits to control mask options,
and cannot be changed in User mode. The erased state are zeros. This register is latched upon
reset going away.
SMD — SLOW Mode at Power-on
When programmed to “1”, this bit enables SLOW mode at power-up. Operating frequency,
fOP=fOSC÷2÷16=fOSC÷32.
SEC — EPROM Security
When programmed to “1”, this bit disables some functions of the Bootstrap mode, preventing
external reading of EPROM content.
TMR2:TMR0 — Power-on Reset Delay
The amount Power-On Reset delay is set by programming these three bits. The delay is selected
as follows:
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Mask Option Register (MOR)
$0FFF
SMD
SEC
TMR2
TMR1
TMR0
RC
unaffected
TMR2
TMR1
TMR0
Delay (Instruction Cycles)
000
256
001
512
0
1
0
1024
0
1
2048
1
0
4096
1
0
1
8192
1
0
16384
1
32768
TPG
88
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參數(shù)描述 |
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