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參數資料
| 型號： | MC68HC05V12CFNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數： | 79/135頁 |
| 文件大?。?/td> | 2080K |
| 代理商： | MC68HC05V12CFNR2 |
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48
XMEGA B3 [DATASHEET]
8074D–AVR–08/2013
28.
LCD - Liquid Crystal Display Controller
28.1
Features
Display capacity up to 25 segment and up to 4 common terminals
Supports up to 16 GPIO's
Shadow display memory gives full freedom in segment update
ASCII character mapping
Swap capability option on segment and/or common terminal buses
Supports from static up to 1/4 duty
Supports static and 1/3 bias
LCD driver active in power save mode for low power operation
Software selectable low power waveform
Flexible selection of frame frequency
Programmable blink mode and frequency on two segment terminals
Uses Only 32 kHz RTC clock source
On-chip LCD power supply
Software contrast adjustment control
Equal source and sink capability to Increase glass life time
Extended interrupt mode for display update or wake-up from sleep mode
28.2
Overview
The LCD controller is intended for monochrome passive liquid crystal display (LCD) with up to 4 Common terminals and
up to 40 Segments terminals. If the application does not need all the LCD segments available on the XMEGA, up to 16 of
the unused LCD pins can be used as general purpose I/O pins.
The LCD controller can be clocked by an internal or an external asynchronous 32kHz clock source. This 32kHz oscillator
source selection is the same as for the real time counter (RTC).
Dedicated Low Power Waveform, Contrast Control, Extended Interrupt Mode, Selectable Frame Frequency and Blink
functionality are supported to offload the CPU, reduce interrupts and reduce power consumption.
To reduce hardware design complexity, the LCD includes integrated LCD buffers, an integrated power supply voltage
and an innovative SWAP mode. Using SWAP mode, the hardware designers have more flexibility during board layout as
they can rearrange the pin sequence on Segment and/or Common Terminal Buses.
Figure 28-1. LCD overview
COM[3:0]
VLCD
BIAS1
BIAS2
Analog
Switch
Array
Shadow
Display
Memory
Control & Swap
Timing
Character
Mapping
CAPH
CAPL
SEG[24:0]
Display
Memory
LCD Power
Supply
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