參數(shù)資料
型號(hào): MC68HC05V7
廠商: Motorola, Inc.
英文描述: 8-Bit Microcontroller Units (MCU).(8位微控制器)
中文描述: 8位微控制器單元(MCU)。(8位微控制器)
文件頁(yè)數(shù): 9/16頁(yè)
文件大?。?/td> 295K
代理商: MC68HC05V7
AN1257/D
MOTOROLA
9
clamp will never be enabled. Although this option is available on the MC68HC705V8 even if the REGEN
mask option is not selected, the user should be very careful about using it if an external power supply is
used to provide 5 volts to the MCU. On the MC68HC05V7, it is not possible currently to select the VDDC
mask option without selecting the REGEN mask option.
The MDLCPU bit (bit 4) in the MOR determines whether the primary regulator can be enabled from
standby mode by a rising edge on the BUS pin. If the MDLCPU bit is programmed to a logic one, a rising
edge detected at either the V
IGN
pin or the BUS pin will cause the primary regulator, if in standby mode, to
be enabled and the V
DD
to V
SSD
clamp, if active, to be released. This allows the user to put the primary
regulator into standby mode to conserve power but still be able to activate the MCU and re-establish
communication over the SAE J1850 serial bus once network communication resumes. If the MDLCPU bit
is programmed to a logic zero, only a rising edge on the V
IGN
pin will cause the primary regulator to exit
standby mode and the V
DD
to V
SSD
clamp to be released. If the REGEN mask option is not selected, the
MDLCPU mask option can still be used to control the operation of the V
DD
to V
SSD
clamp, provided the
supply voltage to the V
BATT
pin is above the specified minimum operating voltage.
The LVR bit (bit 3) in the MOR is used to activate the low voltage reset circuitry on the MCU. If this bit is
programmed to a logic one, the LVR circuit will be enabled, causing the MCU to be held in a reset state
internally whenever the voltage at the V
DD
pins drops below the specified LVR inhibit voltage level (V
LVRI
).
The device will remain in the reset state as long as the voltage at the V
DD
pins remains between the LVR
recovery voltage level (V
LVRR
) and the minimum specified V
DD
voltage level. Below this level, the MCU
operation becomes unspecified.
Once the voltage at the V
DD
pins rises above V
LVRR
,
the MCU will be held in reset internally for 4064 CPU
bus clock cycles. After this internal reset delay, the MCU will exit the reset state and re-enter the active
state. (Refer to the MC68HC705V8 and MC68HC05V7 general release specifications, Motorola document
numbers HC705V7GRS/D and HC705V8GRS/D, for the LVR inhibit and recovery voltage specifications.) If
the LVR bit is programmed to a logic zero, the LVR circuit will not be enabled. The LVR mask option is
available regardless of whether the REGEN mask option is selected.
Miscellaneous Register
The miscellaneous register (MISC, address $002F) is an MCU user register containing two bits which are
used to control operation of the voltage regulator circuit. These bits allow the user to put the primary
regulator into standby mode and to determine the status of the V
IGN
pin. The following descriptions of these
two bits and their operation are applicable to both the MC68HC705V8 and the MC68HC05V7. For an
illustration of the MISC register, refer to Figure 5.
Figure 5. Miscellaneous Register on the MC68HC705V8/05V7
Bit 7
6
5
4
3
2
1
Bit 0
MISC
$002F
Read:
IGNS
OCE
0
0
0
0
0
PDC
Write:
OCE
PDC
Reset:
U
0
U
U
U
U
U
U
= Unimplemented
U = Unaffected
NOTES:
1. Bits 5-1 are unimplemented on the MC68HC705V8 and MC68HC05V7 and always read as zeros.
2. Bit 6 does not affect the operation of the voltage regulator or the LVR circuitry.
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