參數(shù)資料
型號(hào): MC68HC05V7CFNR2
廠(chǎng)商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 157/170頁(yè)
文件大小: 589K
代理商: MC68HC05V7CFNR2
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SECTION 11: 16-BIT TIMER
MOTOROLA
Page 73
MC68HC05V7 Specification Rev. 1.0
11.5.1
ICF - Input Capture Flag
1 - Flag set when selected polarity edge is sensed by input capture edge
detector
0 - Flag cleared when TSR and input capture low register ($15) are
accessed
Reset clears this bit.
11.5.2
OCF - Output Compare Flag
1 - Flag set when output compare register contents match the free-running
counter contents
0 - Flag cleared when TSR and output compare low register ($17) are
accessed
Reset clears this bit.
11.5.3
TOF - Timer Overflow Flag
1 - Flag set when free-running counter transition from $FFFF to $0000
occurs
0 - Flag cleared when TSR and counter low register ($19) are accessed
Reset clears this bit.
11.5.4
Bits 0-4 - Not used
Always read zero.
Accessing the timer status register satisfies the first condition required to clear status bits.
The remaining step is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow function and reading the free-running
counter at random times to measure an elapsed time. Without incorporating the proper
precautions into software, the timer overflow flag could unintentionally be cleared if:
1. The timer status register is read or written when TOF is set, and
2. The MSB of the free-running counter is read but not for the purpose of
servicing the flag.
The counter alternate register at address $1A and $1B contains the same value as the free-
running counter (at address $18 and $19); therefore, this alternate register can be read at
any time without affecting the timer overflow flag in the timer status register.
11.6
TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active if turned on prior
to entering wait mode. If interrupts are enabled, a timer interrupt will cause the processor
to exit the WAIT mode.
11.7
TIMER DURING STOP MODE
In the STOP mode, the timer stops counting and holds the last count value if STOP is exited
by an interrupt. If RESET is used, the counter is forced to $FFFC. During STOP, if the
TIMER is on and at least one valid input capture edge occurs at the TCAP pin, the input
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